
            9/21/89

                                  Application Note

                SWITCHING THE EXTERNAL ROM AND RAM USING THE MC68302


            When designing the MC68302, (or simply the M68000) one of the
            tasks  often required is to switch the locations of  the  ROM
            and  RAM  in the system.  This is because  the  Reset  Vector
            needs  to  be  supplied  from ROM,  while  the  rest  of  the
            exception  vectors are normally included in the RAM, so  that
            they can be modified.  The exception vector area extends from
            $0   to  $FF  (see  p.  2-10  of  the  68302  User's   Manual
            MC68302UM/AD).

            The 68302 makes this easy to do, requiring no additional glue
            logic. To do this, two chip select lines and a few  temporary
            locations  of the Dual-Port RAM are used.  For this  example,
            we assume 256 bytes of EPROM and 68 Kbytes of RAM.

            Conditions at Reset

            We  physically connect CS0 to the ROM and CS1 to the he  RAM.
            After  reset,  the  68302 defaults to having  only  one  chip
            select enabled (CS0), with a base address of $0 (p. 3-42) and
            a  range of 8 Kbytes(p. 3-44).  The ROM should be  programmed
            with an initial set of interrupt vectors and the reset vector
            should  point  to some location within the first 8K  of  ROM.
            CS1  is disabled at reset, so the RAM cannot be accessed  (p.
            3-42).  Also,  the Bsse Address Register (BAR) in  the  68302
            has not been written, so the Dual-Port RAM, and other on-chip
            peripherals   cannot  be  accessed  (p.  2-14).  The   Status
            Register  (SR) of the M68000 core is $2700 (p. 2-3),  putting
            the core in supervisor mode with interrupts masked.  We  will
            leave  the  SR in this condition until the ROM  and  RAM  are
            switched.

            First Things First


            Right now we have the following situation:

            ROM Begins at $0.  Only first 8K is valid for programming.
            RAM Undefined.
            68302 Undefined (except BAR at $0F2 and SCR at $0F4).

            Once  the  reset vector has been taken, the BAR  register  at
            location $0F2 should be written to locate the 68302 Dual-Port
            RAM and on-chip peripheral registers in memory (p. 2-15).  In
            this  example, we will choose $70,0000 as the starting  point
            of  the  4K block of the 68302 and is easily  accessed,  even
            though it overlaps memory with the ROM.  This is because  CS0
            will not activate on accesses to the BAR (p. 5-18).

            Now  that  the 68302 can be fully accessed, the ROM  and  RAM
            chip  selects  can be modified.  First, the  Option  Register
            (OR) of CS0 can be extended to include all 256K  bytes.  This
            is  done  by  writing  the base  address  mask  in  OR0  with
            11111100000b.  At  this time, the DTACK field may be  changed
            to  reduce  the  number of wait states from  6  to  something
            lower.  Also,  while  writing  this  register,  the   Compare
            Function Code (CFC) bit should be cleared, since data  stored
            in  the  program ROM will need to be accessed  and  moved  to
            other  areas  of  memory, as  shown  below.  (At  reset,  the
            function  code for CS0 defaults to 110b to select  Supervisor
            Program and the function code comparison is  enabled).  Thus,
            OR0 could be written with $5F80 for this example.

            Next, the RAM addresses should be defined.  To set the  range
            of  the RAM for 64K bytes to configure it for 0 wait  states,
            to allow both reads and writes, and to disable function  code
            comparisons,  OR1 should be set to $1FE0.  To place  the  RAM
            initially  at $400,000, enable the RAM and set  the  function
            code  to supervisor data, BR1 should be set  to  $A801.  Even
            though the function code is not compared in the assertion  of
            this  chip  select,  it is a good  idea  to  distinguish  the
            function codes for debugging purposes.

            Now that the RAM is enabled, an initial set of vectors may be
            placed  in  it (i.e. copied from the ROM).  Of  course,  they
            will  not  be accessed as vectors until the RAM is  moved  to
            location 0.  Any exceptions that occur during this period  of
            time  will  still  have their vectors derived  from  the  ROM
            vector table.

            We now have the following situation:

            ROM -- $0 to $03FFFF
            RAM -- $400,000 to $40FFFF
            68302 -- $700,000 to $700FFF


            The Switch

            Now it's time to perform the switch.  The way this will  work
            is:  we  will  jump  from  the  ROM  to  the  Dual-Port  RAM,
            reconfigure  Chip Selects 1 and 0 and then jump back  to  the
            ROM.  It  is  important that the RAM be moved first  to  make
            sure  that  an  exception vector  table  is  always  present.
            During  the  brief period while the location in CS1  and  CS0
            overlap, CS0 will take precedence (p. 3-40).


            In  order  to perform the switch we need to execute  a  short
            Dual-Port  RAM  program.  Thus, we copy  the  following  data
            (actually  instructions)  from  ROM  to  the   Dual-Port  RAM
            starting at location $700,000:

            MOVEA #$700834,A1             ; Load BR1 address into A1
            MOVE  #$A001,(A1)             ; Place CS1 at $0 by writing
                                            to BR1
            MOVEA #700830,A1              ; Load BR0 address into A1
            MOVE  #C201,(A1)              ; Place CS0 at $100,000 by
                                            writing to BR0
            JMP   ($Address in ROM).L

            Now, we can execute:

            JMP           ($700,000).L         ; Jump to Dual-Port RAM

            which then causes us to have the following final situation:

            RAM -- $000000 to $00FFFF
            ROM --- $100,000 to $13FFFF
            68302 -- $700,000 to $700FFF

            The initialization of Chip Selects 0 and 1 and the switch  of
            ROM and RAM is now complete.


            Written by:  Robert O'Dell, Moti Kurnick and Yehuda Roudin
