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                                  Application Note

          HOW TO INTERFACE A MASTER 302 TO ONE OR MORE SLAVE 302S



          When more than three  SCC channels are required in an applica
          tion, the idea of using multiple MC68302s to solve the problem
          immediately comes to mind.  One possible solution would be to
          design a board with three fully functioning 302s, each with an
          isolated bus, and the ability to send data and messages between
          them (for instance through a share RAM).  Another approach, how-
          ever, is possible.  Through the 302 "Disable CPU Logic" feature
          (described on p. 3-50 of the MC68302 User's Manual), the 302 can
          be converted into a peripheral device that only requests control
          of the bus for DMA transfers.  Thus, as shown  in Figure 1, a
          single master 302 (i.e. one with the M68000 core enabled) can
          access and control one or more slave 302s (i.e. ones with the
          M68000 core disabled).

          Whether or not to use the "Disable CPU Logic" feature in a mul-
          tiple 302 system depends on the amount of protocol processing
          that is required by the M68000 core, and the data rates of the
          various SCCs.  This application note does not address this issue,
          but rather addresses the design issues that need to be dealt with
          once the performance aspects are deemed reasonable.

          We assume for this example one master 302, and two slave 302s.


          What about Clocking?

          We recommend that the master's clock out (CLKO) line be con-
          nected to the EXTAL  input of the slaves.  This will allow
          the master 302 to perform 0 wait state writes and 1 wait state
          reads from the slave 302 at full 16.67 MHz operation (One wait
          state reads are configured by setting the extra memory wait
          state (EMWS) bit in the SCR registers of the slaves (p. 3-47).
          The states propagation delay between EXTAL and CLKO is 2-11 ns.
          The typical delay is about five ns, and the variance at 25
          degrees C is 3-6.5.

          If operation at 13.5 MHz or below is desired, both the master and
          the slave 302s may use the same clock source, which would then be
          connected to the EXTAL inputs of all three parts.  In Rev B of
          the 302, asynchronous timing will be added that will allow read
          and write accesses with three wait states.  Synchronous accesses
          will still be fully supported.


          Programming the Base Address Registers

          The next issue is how to program the three BAR registers (p. 2-
          15) of the three 302s, considering that they all have the same
          address ($0f2).  Figure 1 shows an easy method of programming
          the BAR registers.  The master 302 first programs its own BAR
          register at $0000f2.  Then for each slave, it pulls the slave's
          P I/O line low and writes to $8000f2 to program the slave's BAR
          register.  This method works because the P I/O lines default as
          inputs to the 302.  After the slave BAR registers are programmed,
          the P I/O lines on the master should be reconfigured as inputs,
          otherwise a contention could occur on the A23 line when a slave's
          DMA is accessing the bus.

          This  method is the easiest because it requires no external glue.
          It costs one P I/O line per slave on the master 302, and reduces
          the address space of each slave's to eight MB, from 16 MB, nei-
          ther of which should be a problem.  If A23 is really needed on
          the slaves, it can be regained, but extra logic is required.


          Dealing with Interrupts

          The following is an example method for the easiest method of
          dealing with interrupts from the slaves.  It assumes that any
          other external interrupt sources are sent directly to the master
          302, without using the interrupt controllers on the slaves.

          * The slaves' internal interrupts cause them to force out level
          four on their IOUT2-0 pins.  (AVEC, RMC and CS0 are not available
          on the slaves).

          * IOUT2 from the slave is connected to the master's PB8, 9, 10,
          or 11 pin (p. 3-31) if the master is in normal interrupt mode,
          or to IRQ1 or IRQ6, if it is in dedicated interrupt mode (p. 3-
          19).  Thus in normal mode the slave interrupts will arrive at
          level four, and in dedicated mode they will arrive at either
          level one or six.

          * During an interrupt acknowledge cycle, the slaves do not supply
          interrupt vectors for any levels (1, 4, 6, or 7).  Rather, the
          master presents the interrupt vector on the bus.

          * The master 302 then reads the slave's interrupt pending reg-
          ister (IPR) to identify the actual interrupt source.

          If you want to use the interrupt controller on a slave 302 (in
          either normal or dedicated mode) to handle interrupt levels one
          six, or seven from an external peripheral, this slave's IOUT2-
          0 pins should be connected directly to the master's IPL2-0 pins.
          The master 302 will supply the vector for levels one, six, and
          seven, and four of the slave will be interpreted as an error
          vector (00000 shown on p. 3-24).  The master 302 software upon
          branching to this vector should then check the slave's IPR
          register to identify the source.

          Arbitration

          If only one slave is present, no arbiter is required, because
          the BR* is an output on the slave which can be sent directly to
          the BR* (input) on the master.  With multiples slaves (i.e.
          multiple external bus masters) external logic must prioritize
          the various BR* requests.  Note also that the BCLR pin from
          each 302 can be used to give the 18 SDMAs in the system, priority
          over the three IDMAs.  (The SDMAs only use the M68000 bus for
          a single bus cycle, so priority between SDMAs is not an issue).

          Written byL  Moti Kurnick, Robert O'Dell

Request MOTsan fax #ap302-3fig. for fiqures. Call (619) 560 5226

                                     M68000 BUS
                                     ----------


                Core Enabled          Core Enabled          Core Disabled
                  (Master)              (Slave)                (Slave)


                  68302 #1              68302 #2               68302 #3



                 PI/O  PI/O             A23                    A23


                                                  Note:  A23 is not used
                                                         by the slaves.


                     To pull-up resistors



                                      Figure 1
                     Programming the Base Address Register (BAR)





                        MICRO CODE EXECUTION FROM ROM AND RAM
                                                      ---


                                    Reset
                 Micro code                       Micro code
                    ROM                              RAM

          0000                              000
                 Scheduler     GOTO ROM           Schedule     GOTO SCH.
                 (Not used)

                                           GOTO RAM
                 Standard      GOTO SCH.
                 Protocol


                                                  Proprietry
                                                  Protocol




                          (set RETURN_RAM flag, push stack)
                                      GOTO ROM

                 Routine1
                            GOTO ROM              Proprietry
                                                  Protocol
                                RETURN (pop stack)
                                 (according to RETURN_RAM flag)


                                                     287

                 Routine2


          2047


