
******************************** 302_ALL.TXT ******************************** 
 
 Documentation
 =============
 
 Documentation Available as of 8/31/90 from your local Motorola sales
 office.
 
1. 68302UM/AD REV1 (68302 User's Manual)
2. 68302UM/AD REV1 User's Manual Errata 8/28/90
3. Rev 0.4 Software Errata 8/26/90
4. 68302 Software Performance 6/18/90.  (Frame throughput using higher
      layer software).
5. Application Notes:
   A.  68302 Buffer Processing and Interrupt Handling. 2/16/90.
   B.  Getting Started with Interrupts on the MC68302.  3/14/90.
   C.  How to Interface a Master 302 to one or more Slave 302s. 4/27/90.
   D.  MC68302 Minimum System Configuration.  8/23/90.
   E.  MC68302...Tied to IDL Bus fors an ISDN Voice Data Terminal. 5/2/90.
   F.  Using the 68302 PCM Mode.  8/14/90.
   G.  An Overview of the Independent DMA in the MC68302.  7/26/90.
   H.  Setting up a UART on the MC68302.  8/27/90.
   I.  Switching the External ROM and RAM Using the MC68302.  8/28/90.
 
 
 Motorola-Developed Software Source Code Available for the 68302 
 ===============================================================
 
 Contact your local Motorola sales office for more information.
 As of 8/31/90:
 
 X.25 Packet Layer Protocol (layer 3)
 LAPB (layer 2)
 LAPD (Layer 2)
 68302 Chip Drivers
 EDX (Event Driven Executive) Real-time Kernel.
 
 
 Special-Purpose RISC Microcodes Available for the 68302 
 =======================================================
 
 Contact your local Motorola sales office for specifications and details.
 As of 8/31/90:
 
 Centronics Transmission Controller.
 SS#7 Controller.
 Profibus Controller.
 
 
 Read-Modify-Write Timing 
 ========================
 Some confusion appears to have arisen over what the AS* and RMC* pins do
 during a read modify write cycle on the 68302.  AS* can be programmed
 to toggle or stay active during the whole cycle depending upon the state of
 the RMCST bit in the System Status bits of the System Control Register but
 the 68302 User's Manual does not have a timing diagram for either type of
 read modify write cycle.
 
 When RMCST = 0, the 68302 performs read modify write cycles just like the
 68000 with AS* asserted for the whole cycle. RMC* also stays active
 throughout the whole cycle.
 
 When RMCST = 1, the 68302 behaves just as though two consecutive memory
 cycles were run (1 read and 1 write), ie. AS* is negated in the middle of the
 cycle and then asserted again for the write. RMC* stays active throughout
 the whole read modify write cycle. This exactly the 68000 TAS (test-and-set)
 instruction cycle.
 
 
 Internal RAM
 ============
 
 There is nothing limiting the use of the internal dual-port RAM to hold
 code for the 68000 core.  Accesses will be zero wait-states from the
 M68000 core.  Make sure that the CFC bit in the BAR register is cleared
 if this mode is used so that both code and data accesses may be made to
 the 68302 on-chip peripheral space.
 
 
 HDLC Receive Address
 ====================
 
 Address recognition on received HDLC data frames can be disabled so that
 the 68302 picks up all of the frames (irrespective of the address) by
 setting all of the bits in the relevant HMASK register to zero.
 
 
 68302 ADI Board
 ===============
 
 What are the advantages of using the host ADI plug-in board instead of
 the serial port on the ADS302 board?
 
 1.  About 15x faster serial downloads.
 2.  Support of downloading more than just s-records (e.g. COFF format)
 3.  Support of 68302 configuration files, that put the 302 and the software
     packages into user-defined configurations.
 4.  Allows user-defined modules to run concurrently with ADS302 board
     software modules.
 5.  Allows a history file "macro replay" facility to record and repeat
     menu-driven sessions.  This is of particular use during hardware debug.
 
 
 
68302 Surface Mount Package
===========================
 
The recommended pad size of the 132-pin FE package is 0.38mm x
1.5mm. This assumes a lead pitch of 0.65mm.
 
 
 
Driving the I2C bus with the 68302
==================================
 
The Philips Inter IC bus (I2C) is similar to the SCP bus on the
68302 and the SCP bus can be used to drive the I2C bus with the
addition of two AND gates and a resistor. However, the minimum
data rate of the SCP (256Kbps) is faster than the I2C maximum
data rate (100Kbps). Therefore the 68302 may be able to drive
certain I2C compatible devices if they can operate at this
higher data rate.
 
 
 
Multiple 68302 Systems
======================
 
If a multiple 68302 or multiple bus  master  with  at  least  one
68302  system  is  being designed, attention must be paid to data
throughput and the location of bottlenecks (in the 68302  CPs  or
on the system bus).
 
As a general rule, the data rates of multiple  68302s,  operating
as  one master and multiple slaves, should scale fairly linearly.
For example, if it is found that three  SCCs  on  one  68302  can
operate   at   256kbps  each,  then  the  six  SCCs  in  a  68302
master/slave configuration  can  operate  at  128kbps  each.  The
decrease  per channel is due to the extra system bus activity and
68000 core activity.
 
If the decrease in SCC performance cannot  be  tolerated  then  a
multiple  68302  master system with multiple system buses will be
needed. In this system there will be no degradation in data rates
and each 68302 can handle the protocol processing for its SCCs.
 
 
 
68302 Thermal Characteristics
_____________________________
 
For the PGA package, Theta jA is 2 degrees C/W.  For the CQFP package,
the Theta jA is 15 degrees C/W.
 
 
 
|          68302 Low Power Modes
|          _____________________
|
|          The  68302  has  three  low power modes: non-destructive low
|          power, destructive low power and lowest power. The first two
|          of these can be completely controlled from software.  In all
          three of these modes  the  68302 peripherals and dual port
          RAM can still be used.
 
|          To enter the non-destructive low power mode, a STOP instruc-
|          tion must be executed with LPEN=1 and LPREC=0. The clock di-
|          vider  (LPCD4 - LPCD0 and LPP16) should be set such that the
|          processor clock is sufficient to  maintain  the  68000  core
|          status  -  in  the case of a 16.67MHz 68302 this is 8MHz. To
|          come out of the non-destructive low power mode, an interrupt
|          must occur and the time taken to come out is the same as  to
|          service an interrupt.
|
|          To  enter the destructive low power mode, a STOP instruction
|          must be executed with LPEN=1 and LPREC=1. The clock  divider
|          (LPCD4  -  LPCD0  and LPP16) can be set to any value but the
|          slower the clock, the less power is consumed.   To come  out
|          of  the  destructive low power mode, an interrupt must occur
|          and the 68000 core will come back up  issuing  a  RESET  for
|          16-31 clock cycles.
|
|          To  enter the lowest power mode, the 68302 must first be put
|          in the destructive low power mode and then the  EXTAL  clock
|          reduced  to, say, 50KHz. Note, the CLKO pin will now also be
|          50KHz and the SCC baud generators and  timers  will  all  be
|          supplied with 50KHz. To come out of this mode, EXTAL must be
|          increased  to  a  frequency sufficient to maintain the 68000
|          core status and then the return is the same as for  the  de-
|          structive low power mode.
 
|
|          68302 LDS*/UDS* Timing
|          ______________________
|
|          The length of the LDS/UDS pulse  during  a  write  cycle  is
|          given by timing spec.  14A and has a minimum length of 60nS.
|          This  is  the  asynchronous  timing  and is dependent on the
|          clock. The synchronous timing is given by specs.  9  and  12
|          and  in  the  worst  case is 60nS (for a 16.67MHz clock). If
|          60nS is not long enough, for example when using LDS*/UDS* to
|          drive a 60nS RAM WE* pin, then it can be extended by slowing
|          down the clock. The width of spec. 14A is 1.5T - 30 nS where
|          T is the clock period (ie. 60nS    at  16.67MHz).
 
 
|          68302 UART Clock
|          ________________
|
|          There is no minimum speed for the external 68302 SCC clocks.
|          This  means  that  a system can be constructed with very low
|          bit rates using the external clock while still  running  the
|          68302 at 16.67MHz.
|
|
|          68302 Enter Hunt Mode Command
|          _____________________________
|
|          Whenever an SCC goes into hunt mode, the character being re-
|          ceived is lost and the receive buffer closed. This  is  true
|          for  all protocols and the hunt mode is used for putting the
|          SCC in a known state part of  the  way  through  a  received
|          frame.
|
|
|          68302 CLKO Loading
|          __________________
|
|          The  50pF CLKO  load in the 68302 User's Manual relates only
|          to timing specification 5A. CLKO can drive a higher capacity
|          with a higher delay (rise and fall time). Simulation of  the
|          device  has  shown that for CLKO loading of 130pF, the EXTAL
|          to CLKO delay is 13nS max.
|
|
|          68302 NRZI Decoding in HDLC Mode
|          ________________________________
|
|          It should be noted that there are in fact  two  versions  of
|          NRZI  around:  NRZI-Space  and  NRZI-Mark.  The  68302  uses
|          NRZI-Space where a binary zero is represented with a  change
|          in  the  signal at the beginning of the bit period and a one
|          has no change.
|
|
|          Driving the 68302 EXTAL Input
|          _____________________________
|
|          The  EXTAL  input  specification  calls for either a crystal
|          circuit or a CMOS level oscillator module  with  tight  rise
|          and  fall  times.  In  order  to achieve these rise and fall
|          times, some external logic may be needed.  The  MC88913  and
|          MC88914  clock  drivers  meet  this  specification  but  the
|          oscillator circuit given on page 3-47 is a cheaper  solution
|          from which CLKO can drive other parts of the system. The ADS
|          board  uses  an  HCT  gate  to drive EXTAL but some HCT data
|          books do not appear to specify output rise and fall times. A
|          similar situation exists with the Motorola  FACT  (74ACT...)
|          and  IDT  FCT (74FCT...) devices which could be used. All of
|          these logic families typically  meet  the  specification  as
|          long as the loading is only the 68302 EXTAL pin.
|
|          Another  solution could be the 74F803 clock driver chip. The
|          TTL outputs will require pull-up resistors in order to drive
|          CMOS inputs.
|
|
|          68302 Serial Channel Latencies
|          ______________________________
|
|          After the ENT bit is set  in  a  transmit  BD,  there  is  a
|          latency of about ten serial clocks before the first data ap-
|          pears  on  the output pins.  Exact figures are not available
|          as the latency depends upon CP loading, bus loading,  proto-
|          col  etc. As soon as ENR is set, data can begin clocking in,
|          so the first data appears in the receive data  buffer  after
|          about 8 or 16 receive clocks depending upon the protocol.
|
 
|          68302 UART Mode with Address Bit
|          ________________________________
|
|          When  the  address  bit  is included in a UART character for
|          multidrop configuration, the A bit is included in the parity
|          calculations.
|
 
|          68302 Supports Bus Cycle Retry
           ______________________________
|
|          Although not mentioned in the User's Manual, the 68000  core
|          of  the  68302  does  support bus cycle retry when BERR* and
|          HALT* are asserted. It is the same as on a MC68000. The IDMA
|          and SDMAs also support the retry function.
|
|
|          Tying the 68302 AVEC pin active
|          _______________________________
|
|          On the 68302, AVEC* should not be tied low  permanently  be-
|          cause  the internal state machines will then see both DTACK*
|          and AVEC* active during every bus cycle  which  can  put  he
|          state  machine into an undetermined state, especially during
|          an interrupt acknowledge cycle. Also, when the interrupt ac-
|          knowledge cycle for an internal 68302 peripheral  (level  4)
|          is  running,  it could cause an autovector instead of normal
|          vector operation.  Normally the autovector need not be used
           on the 302, since vectors are provided for up to 7 external
           interrupt sources (IRQ1*, IRQ6*, IRQ7*, and PB8-11).
|
|
|          Resetting the 68302 Internal Peripherals
|          ________________________________________
|
|          The 68302 User's Manual (page 5-4) states that  the  SIB  is
|          almost  fully reset by a RESET instruction. Referring to ta-
|          ble 2-9 on page 2-19, a number of entries are marked with an
|          asterisk. These registers are only reset by a  total  system
|          reset  (RESET*  and  HALT* pins both active) and not after a
|          RESET instruction when the other registers are reset.
|
|          For  example,  the  GIMR  and IPR are both reset with $0000
|          during a total system reset, but after a  RESET  instruction
|          GIMR is unaffected, while IPR is reset with $0000.
|
|
|          68302 in Slave and Low Power Modes
|          __________________________________
|
|          When the 68302 is used in slave mode (DISCPU high), the core
|          still  consumes current. This current can be reduced by put-
|          ting the slave into low power mode which is  possible  since
|          the master can access the slave's SCR. To put a master 68302
|          into  a  low  power  mode, you normally write to the SCR and
|          then run a STOP instruction - this STOP is not needed  on  a
|          slave.  A  master 68302 will then come out of low power mode
|          after on an internal interrupt but this does not  happen  in
|          slave  mode because some extra logic has been added in order
|          to detect such a situation.
|
|          Note, in order to get the absolute lowest power,  the  EXTAL
|          clock frequency must be reduced and this is also true of the
|          slave. This will affect the baud rate generators and timers.
|
||
|
|          Generating DTACK in a Master/Slave 68302 System
|          _______________________________________________
|
|          In  a  system  where there is a master 68302 and one or more
|          slave 68302s, the DTACK* lines of all devices  can  be  tied
|          together and have one pull-up resistor. This can be done be-
|          cause  DTACK*  is  a  tri-state  line  (as well as being bi-
|          directional) and remains tri-state  whenever  it  is  not  a
|          driven output. In this way, the chip select logic in one de-
|          vice  can  be  used for address decoding bus cycles from an-
|          other device. The only condition is  that  the  chip  select
|          logic in two devices must not overlap address ranges.
|
|
|
|          Timing Specs. for an External Master Doing a Sync Access
|          ________________________________________________________
|
|          The minimum values of timing specifications 116 and 118  are
|          0nS from falling S6 and rising S0 respectively.  Also, specs
           115 and 117 are particularly critical for synchronous opera-
           tion.  R/W* must be clocked in by the 68302 during rising S4,
           and no earlier.  Similarly, UDS/LDS* must be clocked in by
           the 68302 during rising S6, and no earlier.
|
|
|
|          68302 IDMA Internal Limited Bandwidth
|          _____________________________________
|
|          When  the  68302  IDMA  is  run in the internal limited rate
|          mode, the IDMA will occupy the bus until it has used up it's
|          allocation of the bandwidth in a 1024 clock period. For  ex-
|          ample, if the IDMA is given 75% of the bus time, it will use
|          the  bus  for 768 clocks and then give it up for 256 clocks.
|          These are approximate figures and the exact  figures  depend
|          on  how  many  SDMA accesses and interrupts occur.  The IDMA
|          will never use more than it's allocated  percentage  of  the
|          bus  but may use less if it is interrupted or SDMAs need the
|          bus.
|
|          68302 IDMA and Interrupts
|          _________________________
|
|          If the 68302 IDMA has control of the bus when  an  interrupt
|          arrives, the bus arbiter gives the bus to the 68000 core for
|          interrupt  handling.  When  the  interrupt  service  routine
|          clears the IPA bit in the SCR, the bus is handed back to the
|          IDMA which continues from where it was before the  interrupt
|          if  there is a transfer request pending. There is no need to
|          re-start the IDMA from a known point.
|
|
|          68302 Master-Slave Vector Generation
|          ____________________________________
|
|          When connecting a master 68302  to  a  slave  68302  (rev  B
|          silicon),  we  suggest that users do not program the VGE bit
|          on the slave. It they do, there will be a collision  between
|          the  master's level 4 interrupts and the slave's level 4 in-
|          terrupts. This could be "fixed" by tricking the  slave  into
|          thinking  that  another interrupt level is level 4. However,
|          this adds logic which slows down the interface and adds  ex-
|          pense.  VGE  was  designed for use with a processor like the
|          68020 to be the master and the 68302 to be the only slave.
|
|          The user is best off allowing the master 68302 generate  one
|          vector for the whole of the slave 68302 and then reading the
|          slave's  IPR  register  to  determine  the  actual interrupt
|          source. This only adds a few software instructions.
|
|          68302 and the SDLC Protocol
|          ___________________________
|
|          There are four major differences between HDLC and SDLC which
|          need to be addressed when the 68302 is to be used in a  SDLC
|          network. These are:
|
|          1.  HDLC  uses an 8-bit address field with options to extend
|          this.  SDLC always uses only one byte.
|
|          2. HDLC can have an extended control field but  SDLC  always
|          has one byte here.
|
|          3.  SDLC  always has an even number of bytes in the informa-
|          tion field.
|
|          4. SDLC provides some extra commands that HDLC does not.
|
|          Since the 68302 CP is only concerned with  the  framing,  it
|          can  be  seen  that  it is within the scope of the device to
|          generate SDLC frames. Using the HDLC address selection  reg-
|          isters,  it is possible for the 68302 to selectively receive
|          SDLC frames depending on the  SDLC  address  and/or  control
|          fields.   This   cannot   be   done   with   extended   HDLC
|          address/control fields. Item 4 in the above list is  handled
|          by software in the 68302 CPU.
|
|          The SNA network protocol from IBM is based on SDLC frames so
|          it  follows that the 68302 can be used in a SNA network with
|          suitable software.
|
 
|          68302 PCM Framing
|          _________________
|
|          When using the 68302 in PCM mode, there is no restriction on
|          the number of bits which can be enveloped by the  L1SY0  and
|          L1SY1  signals.  The  enveloped bits on the receive line are
|          interpreted by one of the SCC protocols and then packed into
|          bytes before being transferred to memory by the SDMA.
|
|          For example, if two bits are always enveloped and the SCC is
|          in HDLC mode then zero insertion/deletion  is  performed  on
|          the enveloped bits.  The bits are then packed into bytes and
|          are  considered  one  frame  when the closing flags arrives.
|          Since HDLC  bytes  are  transmitted  least  significant  bit
|          first,  the first two bits received will be D0 and D1 of the
|          first byte and the next two bits enveloped will  be  D3  and
|          D4.  When two bytes have been formed, the SDMA will transfer
|          the  word  to memory. The same system applies in reverse for
|          transmit.
|
|          It is possible to envelope more than one PCM channel onto an
|          SCC and then software can sort out  which  bits  are  which.
|          However, this is not a good idea for protocols like HDLC be-
|          cause the SCC will get confused when calculating the CRC. In
|          order to receive more than one PCM channel on a SCC, the SCC
|          should be in totally transparent mode.
|
 
|          68302 ADS Board in Slave Mode
|          _____________________________
|
|          The 68302 ADS board was not designed to work with DISCPU as-
|          serted.
|
 
|          Linking the 68302 and MC145488 DDLC
|          ___________________________________
|
|          An  elegant way of providing two extra high speed HDLC chan-
|          nels with a  68302 is to put a MC145488 DDLC into  the  sys-
|          tem.  The  DDLC  has a DMA controller on board which handles
|          data transfers between itself and memory.  However,  in  the
|          worst  case,  the DDLC can output AS* and address simultane-
|          ously. If the chip select logic is being used to select  the
|          memory  that the DDLC's DMA is accessing, 68302 timing spec-
|          ification 162 could be violated.
|
|          If the DDLC has a clock frequency of  less  than  7MHz  then
|          there  should  not be a problem because the relevant DDL re-
|          lated to the clock period. If the DDLC has a clock frequency
|          greater than 7MHz then some delay needs to  be  inserted  on
|          the  DDLC's  AS*  line. When running the DDLC at 16MHz, this
|          delay should be greater than 15nS.
|

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