 
                  302APPS2 - Various applications hints  
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68302 Mask Revisions 
==================== 
  
There has been some confusion about what mask devices belong to which 
revision of the functional specification of the 68302. The table below 
should clear this up:- 
  
Mask   Functional Revision 
=================================================================== 
SAMPLE    Rev A      These were the very first samples shipped. 
1B14M     Rev A.1    Only a slight change from  Rev A devices. 
2B14M     Rev B      First Rev B silicon but not very many shipped. 
3B14M     Rev B      The latest silicon -- still Rev B. 
  
The 68302 Rev 1 Users Manual describes Rev B silicon which contains 
some new functions, such as the DRAM refresh controller, which were 
not available on the Rev A and A.1 devices. 
  
68302 Internal Vector Fetch 
=========================== 
  
When the 68302 interrupt controller is providing a vector, the whole 
cycle will be seen on the address bus and function control pins and 
IAC will be high. For example, if the interrupt controller provides a 
level 7 vector, the FC pins will all be high, A1-A3 and A19-A16 are 
all high and IAC is high. 
 
 
68302 Lowest Power Mode 
======================= 
  
The following steps give a simple way to enter and exit the lowest 
power mode on the 68302:- 
  
1.  Set the lower byte of the SCR (location $F7) to $FF. 
2.  Disable all interrupts except PB11 in the IMR. 
3.  Turn off any unneeded peripherals, such as the SCCs by clearing 
    the ENR and ENT bits. 
4.  Start off a timer to toggle a pin in 20 clocks or so. 
5.  Execute the STOP instruction. 
6.  Use the toggled pin to reduce the clock rate to around 50 KHz. 
    Ensure no glitches occur on the EXTAL signal which exceed the maximum 
    clock frequency. 
7.  Power consumption should be lowest now. 
8.  A wake-up signal comes from the system. 
9.  Wake-up signal increases the clock frequency to 8-16 MHz and then 
    pulls PB11 pin low.  (Can happen simultaneously if desired). 
10. 302 then generates interrupt and 68302 reset is automatically 
    generated by the low power re-awake logic. 
11. 68302 is reset, and s/w processing continues. The 68000 registers 
    are reset but Dual-port RAM is still intact. 
  
68302 Baud Rate Generators in Low Power Mode 
============================================ 
  
When the 68302 is put into low power mode, the SCC internal baud rate 
generators should be disabled by setting the EXTC bits in the SCON 
registers. This saves about 4mA (at 16.67MHz) per SCC. Note, by 
default EXTC is cleared. 
  
68302 Capacitance De-Rating 
=========================== 
  
The timing specifications given in the 68302 User's Manual for the 
68000 core pins are with a load of 130pF. If the load on these pins is 
less, subtract 0.035nS for every pF less than 130pF for 68302 core 
pins except CLKO. This rule works down to a load on the pins of 50pF 
and these figures are guaranteed by the design of the 68302. The 
derating notes given in some of the timing specification tables are 
still applicable. 
  
68302 Timing Specification 20 
============================= 
  
Timing diagram Figure 6-3 in the 68302 User's Manual shows the end of 
the timing spec 20 arrow incorrectly. The description is correct. 
  
68302 Serial Loopback Control 
============================= 
   
When all three SCCs on the 68302 are in NMSI mode, they can be 
individually put into loopback mode using the DIAG bits in the SCC 
mode registers but data will still appear on the TXD pin. In order to 
make the TXD2 and TXD3 pins high or low, they should be switched over 
to function as output ports. If TXD2 or TXD3 need to be tri-state, 
they should be switched over to function as input ports. 
  
The SDIAG bits in the SIMODE register control SCC1 and the other SCCs 
only if they are programmed to a multiplexed mo@%$(PCM, IDL or GCI). 
Using the SDIAG bits to control loopback tri-states the TXD1 pin and 
drives a '1' onto the others when they are programmed to a multiplexed 
mode. 
  
68302 Abort Character 
===================== 
  
The Abort character is sent out when the stop transmit command is 
issued to an SCC in HDLC mode. Whenever the Abort character (7 ones) 
is sent out, it is always preceded with a zero. This is useful in the 
DMI Mode 3 US ISDN protocol. 
  
68302 FIFO Lengths 
================== 
  
The transmit FIFO length is 4 words in HDLC and transparent modes, and 
the receive FIFO is 3 words in HDLC and transparent modes.  For the 
other protocols, substitute bytes instead of words. 
  
68302 Lock Stepping 
=================== 
  
Some applications of the 68302 require two or more devices to act 
synchronously, for example in a fault tolerant system. The 68302 has a 
special feature to allow this. If the FRZ* pin of the devices to be 
synchronised is pulsed during reset, they will become synchronised 
thereafter, even for interrupts and bus arbitration. Unlike the 68020, 
there are no internal registers which must be set up by running a 
special stream of instructions. 
  
The CP of the 68302 is a microcoded engine so two CPs will stay 
synchronised provided they are given the exact same set of stimuli 
signals and commands together. Once the two 68302s are in step, all of 
inputs signals must meet the setup times (time spec 47 for the core) 
but ensure that the signals do not come is too early so that they 
could be recognised by one 68302 a cycle before the other. 
  
The microcode's operation is deterministic but it services SCC 
requests. The SCC clocks are asynchronous to the core clock so special 
attention needs to be given to ensure that SCCs on separate 68302s are 
synchronised. When the SCCs are not synchronised the microcode will 
not be. Furthermore, the DMA bus cycles depends on the core arbiter 
which need to be synchronised. The SCCs and BRGs can be synchronised 
when the SCON and SCM registers on both devices are written at the 
same time. Take care of external clocks to the SCCs, they are 
asynchronous to the parallel clocks and should be within their set up 
timing  ranges. 
  
Note, this feature is only available on revision B devices and all 
devices which are to be synchronised must be of the same mask set. 
  
The following timing for the FRZ* pulse should be used:- 
  
CLKO       I--I  I--I  I--I  I--I  I--I  I--I  I--I  I--I  I--I  I-- 
          -I  I--I  I--I  I--I  I--I  I--I  I--I  I--I  I--I  I--I 
  
RESET* and                                                   I------ 
HALT*      --------------------------------------------------I 
  
                      Tsu              Th 
FRZ*       -----------I      T1        I---------------------------- 
                      I----------------I           Td 
  
{_FRZ* width low (T1) is 2 clocks minimum, 
FRZ* set up time to CLKO rising edge (Tsu and spec 205) is 20nS minimum, 
FRZ* hold time from CLKO high (Th and spec 206) is 10nS minimum and, 
FRZ* high to HALT*/RESET* high (Td) is one clock minimum. 
  
When VCC and the clock, RESET* and HALT* lines are stable FRZ* can go 
low. 
  
68302 LAPD/LAPB Software 
======================== 
  
Currently the 68302 LAPD and LAPB software (rev 4) can only handle 
three channels but this will be increased to 12 in the next revision. 
This will allow a master processor to handle the level 2 protocol for 
all serial channels from four 68302s. The chip driver software is not 
a problem since it can already drive eight 68302s. 
  
 
 
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