Cache controller fur ATARI ST
GAL 2: Cache und Bussteuerung

*identification
CCDT2V6;

*type
GAL16V8;

*pins

/PAS    = 1,            % verzogertes AS-Signal         %
/UDS    = 2,			% Upper Data Strobe (prozessor) %
/LDS    = 3,			% Lower Data Strobe (prozessor) %
/WR     = 4,            % Read/Write                    %
/AS     = 5,            % Address strobe (prozessor)    %
 CEN    = 6,			% Cache ein-aus					%
 MEM    = 7,            % RAM/ROM-Zugriff               %
/BGACK  = 8,			% Bus Grant ACKnowledge			%
 HIT    = 9,            % Cache-Treffer                 %
 EN_I   = 11,			% Cache Enable (Ruckkopplung)   %
 ENAB.T = 12;           % Cache Enable (Ausgang)        %
/CWE.T  = 13;			% Write Enable Cache-RAMs		%
/LDWE.T = 14;			% Write Enable unteres Daten RAM%
/UDWE.T = 15;			% Write Enable oberes Daten RAM %
/BLDS.T = 16,			% Lower Data Strobe (bus)       %
/BUDS.T = 17,			% Upper Data Strobe (bus)       %
/BAS.T  = 18,			% Address Strobe (bus)			%
/DOE.T	= 19,			% Output Enable Daten-RAMs		%

*boolean-equations

 BAS.E = /BGACK;
 
 BAS = AS & PAS & /EN_I
 	 + AS & PAS & /MEM
 	 + AS & PAS & WR
 	 + AS & PAS & /HIT
 	 + AS & BAS;
 	 
 BLDS.E = /BGACK;
  
 BLDS = PAS & LDS & /EN_I
 	  + PAS & LDS & /MEM
 	  + PAS & LDS & WR
 	  + PAS & LDS & MEM & /WR & /HIT
 	  + PAS & UDS & MEM & /WR & /HIT
 	  + LDS & BLDS
 	  + UDS & BLDS;
 	  
 BUDS.E = /BGACK;
 
 BUDS = PAS & UDS & /EN_I
 	  + PAS & UDS & /MEM
 	  + PAS & UDS & WR
 	  + PAS & UDS & MEM & /WR & /HIT
 	  + PAS & LDS & MEM & /WR & /HIT
 	  + UDS & BUDS
 	  + LDS & BUDS;
 	  
 CWE = EN_I & BAS & ( UDS + LDS ) & MEM & /WR & /HIT
	 + ( UDS + LDS ) & CWE;
	 
 DOE = ( UDS + LDS ) & MEM & /WR & HIT & /CWE & EN_I;
 
 UDWE = EN_I & PAS & ( UDS + LDS ) & MEM & ( /WR & /HIT + WR & UDS & HIT )
      + ( UDS + LDS ) & UDWE ;

 LDWE = EN_I & PAS & ( UDS + LDS ) & MEM & ( /WR & /HIT + WR & LDS & HIT )
      + ( UDS + LDS ) & LDWE ;
      
 ENAB = /AS & CEN + AS & EN_I + CEN & EN_I ;
      

*end

	 	 



