Cache controller fur ATARI ST
GAL 3: DTACK Steuerung und Cache Loschlogik
(nur zum Entwurf)

*identification
CCDT3V8;

*type
GAL16V8;

*pins

 CL8    = 2,            % 8 Mhz Takt                    %
/SDT    = 3,            % System DTack                  %
/FCS    = 4,            % Fpu Chip Select               %
/RESET  = 5,            % Reset                         %
/BGACK  = 6,			% Bus Grant ACKnowledge			%
 MEM    = 7,            % RAM/ROM-Zugriff               %
/WR     = 8,            % Read/Write                    %
 HIT    = 9,            % Cache-Treffer                 %
 ST0.R  = 12,           % Bit 0 der Zustandskodierung   %
/PDT.T  = 13,           % Prozessor Dtack				%
 ST1.R  = 14,           % Bit 1 der Zustandskodierung   %
 ST2.R  = 15,           % Bit 2 der Zustandskodierung   %
/PAS.R  = 16,           % verzogertes AS-Signal         %
/CLR.T  = 17,			% Cache-Loschsignal				%
/AS.T   = 18,           % Address strobe (Eingang)      %
 ENAB.T = 19;           % Cache Enable (Eingang)        %

*boolean-equations

 ENAB.E = GND ;
  
 AS.E = GND ;
 
 CLR = BGACK + RESET + /ENAB ;
 
 PDT = ST2 & /ST1 & /ST0 & PAS		% Zustand S5 %
 	 + ST2 & /ST1 &  ST0 & PAS		% Zustand S6 %
 	 + ST2 &  ST1 &  ST0 & PAS		% Zustand S8 %
 	 + FCS & AS & SDT;				% FPU-Zugriff %
 	 
	 ST0 = AS & /RESET & /FCS & /PAS
	 	 + AS & /RESET & ST1 & /ST0
	 	 + AS & /SDT & /RESET & /ST2 & ST1
	 	 + AS & /CL8 & /RESET & /ST2 & ST1
	 	 + /RESET & ST2 & /ST0
	 	 + AS & /WR & /RESET & ST2 & ST1;
	 	 
     ST1 = AS & MEM & HIT & /WR & ENAB & /RESET & /FCS & /PAS
         + AS & /RESET & /FCS & /ST2 & /ST1 & ST0
         + AS & /RESET & ST1 & /ST0
         + AS & /SDT & /RESET & /ST2 & ST1
         + AS & /CL8 & /RESET & /ST2 & ST1
         + AS & /WR & /RESET & ST2 & ST1;
         
     ST2 = AS & MEM & HIT & /WR & ENAB & /RESET & /FCS & /PAS
         + AS & SDT & CL8 & /RESET & /ST2 & ST1 & ST0
         + /RESET & ST2 & /ST0
         + AS & /WR & /RESET & ST2 & ST1;
         
    /PAS = RESET
         + ST2 & /ST1 & ST0
         + WR & ST2 & ST1
         + /AS & ST0
         + /FCS & /ST2 & /ST1 & /ST0 & PAS
         + /AS & /ST2;

*end

	 	 



