HARDWARE.TXT                                         ThR
                                              2002-03-11


General

Both the EtherNEA and EtherNEC interfaces generate the signals for a
standard PC 8-bit ISA bus connector. Although the NE2000 cards are
16-bit cards they work also in an 8-bit slot. This is documented in
some of the original NE2000 design papers. It was meant in those days
a "new" NE2000 card to work in the original PC which had an 8bit only
bus (we have come a long way).  Thus do not worry that the small 16bit
extension edge connector of a NE2000 (clone) card will be free
floating.  Please note that the interfaces only provide for the
signals necessary to run a NE2000. They do not provide a generally
usable ISA slot.


EtherNEC hardware

EtherNEC is an adapter from the Atari Cartridge Port (ROM port, CP) to
a 8-bit ISA bus.

Hardware circuit description (see directory ETHERNEC for schematics)

As there is no reset line on the CP, a resistor and a capacitor are
used to reset the NE card on power up.

Reading from the NE card is done by a read cycle on the CP at address
/ROM4 + 512*ISA address as the ISA address lines A0-A4 are connected
to CP A9-A13. /ROM4 going low will start the ISA read cycle, enable
the ISA bus buffers of the NE card and start decoding of the ISA IO
address by the NE card. /ROM4 going high ends the cycle and the
processor latches the data.

Because the CP is read only writing to the NE card must be done with
the trick to read from addresses that stand for the data. Dummy reads
at /ROM3 base address + data*2 + ISA address*512 effect this. You
might wonder why everything appears to be shifted up one bit. There is
no CP "A0" address line. There are the signals /UDS and /LDS instead
typical for the 68000 family. The original design which generated an
"A0" worked on an ST and an STE but did not on a Falcon.

The falling edge of /ROM3 enables the CP address lines A1-A8 onto the
data bus and starts the ISA write cycle. The rising edge will end the
ISA write cycle and the NE latches the data. The processor will also
see and just read this same data but that is harmless.
Elmar Hilgart reported that the bus buffer IC shall be an TTL F-type
to keep up with the fast cycles on the Falcon. 

To reduce physical stress on the CP and allow for the NE card to stand
upwards or lay flat, Lyndon designed an adapter from the 2mm CP to
2.54 mm connectors for 40pin standard ribbon cable (please see the
layouts in folder ETHERNEC) to attach the EtherNEC adapter. This cable
should be as short as possible as the processor bus runs on it
unbuffered! (15cm max.)

Power +5V for the EtherNEC adapter and the NE card is taken from +5V
at the CP. +12V do no seem to be necessary unless you want to run
"thick ethernet" cable.



EtherNEA hardware

EtherNEA is an adapter from the Atari ACSI bus to a 8-bit ISA bus.

Hardware circuit description (see directory ETHERNEA for schematics)

The interface circuit is directly connected to the ACSI port.  It does
not provide any buffering. Thus the cable to the ACSI shall be as
short as possible (50cm max). If another device is hooked to the ACSI
bus please connect the interface to the ACSI output of that device.

The ISA port is hardwired to work at an IO address of 0x300.  When
writing to the ACSI bus and ACSI-A1 was set Low the '02 NOR gate
output gets HI and the '373 latches the ACSI port address in the upper
three bits and the lower 5 bits to be used as the lowest 5 bits of the
ISA IO address. The '138 decodes the ACSI-port address. The jumpers
J1, J2, J3 allow to set the ACSI port address of the interface. Note
that J3 selects the ACSI port address from either 0 to 3 or 4 to 7. J1
and J2 must be set consistently to choose from 0,1,2,3 or 4,5,6,7
depending on J3.

In the prototyping phase it turned out that reads and writes to the
ACSI port are too fast for the read and write cycles of some of the
NE2000 cards I was testing. These were all old multi chip cards. As
there is no capability to prolong the read or write cycles for single
byte reads or writes on the ACSI bus, quite an unusual hardware
solution was employed. A1 low will also set the two d-flip-flops '74
to a known initial state (no ISA read or write). The first write to
the ACSI port will initiate an ISA write and the second ACSI write
will terminate the ISA write. Similar procedure is done for reads.

A new NE2000 clone with a single Realtek 8019AS chip turned out to run
directly from the outputs of the '138. With jumpers J4 and J5 you can
choose between this fast mode (/IOR, /IOW coming from the '138) or
slow mode described above. Note that you must select the appropriate
driver to fit the hardware jumper setting: ENEAF.STX or ENEAF.MIF for
fast mode and ENEAS.STX or ENEAS.MIF for slow mode.


The third NOR gate '02 is used to invert the ACSI ~RESET to the RESET
signal needed on the ISA bus.

The forth '02 is simply used to generate a logical Hi signal to
connect to inputs that require a constant logical Hi level.  This is
safer than connecting the inputs to +5 Volt in case of accidental
short circuits on the board or during testing measurements (a short
circuit of an output to +5 Volt is usually lethal to that IC).

I built the interface prototype in wire wrap technique. As the
interface is simple, a one-sided printed circuit board layout should
be possible. Please note that if you develop such a printed cicuit
board layout for this interface you must also publish it under the
public under the GNU public license and send it to me so that I can
include it into this package.

A NE2000 compatible card requires +5 Volts power supply. +12 Volts
supply only seems to be needed if you use "thick ethernet" which is
seldom used today.  Rather most people today use twisted pair and some
still use koax cable.

The interface needs +5 Volts. As my Atari ST is housed in a tower
cabinet I connected the hardware to a power connector of the standard
power supply forseen for a harddisk.
