**************************************************************************
*																		 *
*								   						 *
* =====================================================================  *
*  A T A R I  -  F A L C O N  -  H A R D W A R E  -  R E G I S T E R S	 *
* =====================================================================  *
*																		 *
*																		 *
*			  T R Y   O F	D O C U M E N T A T I O N	B Y 			 *
*																		 *
*						 A E O N   &   C H R I S						 *
*																		 *
*							  O F	A U R A 							 *
*																		 *
*						 VERSION 0.4  (11.04.93)						 *
*																		 *
*						 FIRST OFFICIAL RELEASE 						 *
*																		 *
**************************************************************************

For any questions and donations write to:

								AURA
								PLK 019200 C
								W-7600 OFFENBURG
								GERMANY

If you have found some new things about the hardware just contact us.
Don't forget to include international reply coupons if you expect an
answer.

Remember:
Donations will force us to release more informations about the hardware.


signing:				AEON/CHRIS OF AURA 


----------------------------------------------------------------------------

******: seems to be unused
new   : new FALCON-adresses
new<==: perhaps new FALCON registers
<=====: new FALCON registers

****************************************************************************
IDE - PORT (FALCON) 
****************************************************************************

$FFF00000		[R/W] <=====
   :		 :	   :
   :		 :	   :
$FFF0003F		[R/W] <=====

****************************************************************************
MEMORY - MANAGEMENT
****************************************************************************

$FFFF8001.b [R/W]		Memory-Configuration

****************************************************************************
???
****************************************************************************
$FFFF8005.b [R/W]			76______	Monitor-Type
							||
							00		 SM124 
							01		 SC1435 
							10		 VGA und SYNC-Monitore
							11		 TV

$FFFF8007.b (R/W)			__5_3__0	Hardware-Flags
							  | |  + Taktfrequenz 0= 8	 / 1= 16 MHz
							  | +--- Blitter	  0= ein / 1= aus
							  +----- Register	  0= ein / 1= ausblenden
		
****************************************************************************
VIDEO - SYSTEM
****************************************************************************

$FFFF8201.b [R/W]						Videoadresse Hi
$FFFF8203.b [R/W]						Videoadresse Mi
$FFFF820D.b [R/W]						Videoadresse Lo

$FFFF8205.b [R/W]						Videoadresszhler Hi
$FFFF8207.b [R/W]						Videoadresszhler Mi
$FFFF8209.b [R/W]						Videoadresszhler Lo

$FFFF820A.b [R/W]			______10	Syncmode
								  ||
								  |+ 1: external clock
								  |  0: internal clock
								  +  set to one (ex-50/60 Hz-Bit)

$FFFF820E.w [R/W]	_______876543210	Line-Wide
This register is used to configure the word-distanz from the end of 
one to the begining of the next graphic line. 


$FFFF8210.w [R/W]	______9876543210	Vertical-Wrap
This register is used to configure the word-lenght of one graphic line.

					FEDCBA9876543210
					____rRRRgGGGbBBB rgb lowest Bit 
$FFFF8240.w [R/W]						ST Color $00
  :  :	:								:  :  :  :	
$FFFF825E.w [R/W]						ST Color $0F

$FFFF8260.b [R/W]			______10	ST-Shift
								  ||
								  00 ST-Lowres
								  01 ST-Medres
								  10 ST-Highres
								  11 not defined

$FFFF8265.b [R/W]			____3210	Horizontal-Scroll
								||||
								++++ 0-15: left shifted pixel

$FFFF8266.w [R/W]	_____A_8_654____	Falcon-Shift
						 | | |||
						 | | ||+---- 1: 256-color mode
						 | | |+----- 0: internal vertical sync
						 | | |		 1: external vertical sync
						 | | +------ 0: internal horizontal sync
						 | |		 1: external horizontal sync 
						 | |
						 | +-------- 1: True-color mode
						 +---------- 1: 2-color mode

$FFFF8280.w [R/W]	______9876543210	Horizontal-hold-counter
$FFFF8282.w [R/W]	______9876543210	Horizontal-hold-timer
$FFFF8284.w [R/W]	______9876543210	Horizontal-border-begin
$FFFF8286.w [R/W]	______9876543210	Horizontal-border-end
$FFFF8288.w [R/W]	______9876543210	Horizontal-display-begin
$FFFF828A.w [R/W]	______9876543210	Horizontal-display-end
$FFFF828C.w [R/W]	______9876543210	Horizontal-SS
$FFFF828E.w [R/W]	______9876543210	Horizontal-FS
$FFFF8290.w [R/W]	______9876543210	Horizontal-HH

$FFFF82A0.w [R/W]	_____A9876543210	Vertical-frequenz-counter
$FFFF82A2.w [R/W]	_____A9876543210	Vertical-frequenz-timer
$FFFF82A4.w [R/W]	_____A9876543210	Vertical-border-begin 
$FFFF82A6.w [R/W]	_____A9876543210	Vertical-border-end 
$FFFF82A8.w [R/W]	_____A9876543210	Vertical-display-begin 
$FFFF82AA.w [R/W]	_____A9876543210	Vertical-display-end 
$FFFF82AC.w [R/W]	_____A9876543210	Vertical-SS 



$FFFF82C0.w [R/W]	_______8_6___2__
						   | |	 |
						   | |	 +-- VGA-Flag
						   | +----- Monochrom Flag
						   +------- Pal-Flag
$FFFF82C3.b [R/W]			_____210	Video-Control
								 |||
								 ||+- 1: Zeilenverdopplung
								 |+-- 1: interlace on
								 +--- 0: 320 pixel horizontal
									  1: 640 pixel horizontal

****************************************************************************
DMA / DISK - CONTROLLER (ST)
****************************************************************************

$FFFF8604.w [R/W]						FDC / Sektor Count
$FFFF8606.w [R/-]						DMA Status 
			[-/W]						DMA Mode 

$FFFF8609.l [R/-]						Count	 (24 Bit)
			[-/W]						DMA Base (24 Bit)

****************************************************************************
PSG - SOUNDCHIP AY-3-8910
****************************************************************************

$FFFF8800.b [R/-]						Read Data
			[-/W]						Register Selection
$FFFF8802.b [R/W]						Write Data

NOTE: The PSG-Registers are now fixed at 2 adreses ($8800.w/ $8802.w). 
Accessing the shadowregisters ($8804.w - $8900.w) cause a buserror.


****************************************************************************
PCM - SOUNDCHIP (CODEC)
****************************************************************************

$FFFF8900.w [R/W]	____32107_54__10	Sound-DMA-Control	 
						||||| ||  ||
						||||| ||  |+ 1: DMA-Play enable
						||||| ||  +- 1: DMA-Play frame repeat
						||||| |+---- 1: DMA-Record enable
						||||| +----- 1: DMA-Record frame repeat
						||||+------- 0: select playframe-adresses
						||||		 1: select recordfame-adresses
						||||
						||||		 MFP-IRQ-7
						||00-------- no request
						||01-------- after playing a frame
						||10-------- after recording a frame
						||11-------- after playing or recording a frame
						|| 
						||			 Timer-A-Request
						00---------- no request
						01---------- after playing a frame
						10---------- after recording a frame
						11---------- after playing or recording a frame

$FFFF8903.b [R/W]						Frame-Start-Address Hi
$FFFF8905.b [R/W]						Frame-Start-Address Mi
$FFFF8907.b [R/W]						Frame-Start-Address Lo 
$FFFF8909.b [R/W]						Frame-Address-Counter Hi 
$FFFF890B.b [R/W]						Frame-Address-Counter Mi
$FFFF890D.b [R/W]						Frame-Address-Counter Lo
$FFFF890F.b [R/W]						Frame-End-Address Hi
$FFFF8911.b [R/W]						Frame-End-Address Mi
$FFFF8913.b [R/W]						Frame-End-Address Lo

HOW to access the play/record-frame:
You have to set bit 7 of $8901.w to select the play- or record-shadow-
register, then access the frame-begin/end-registers! The play- and 
record-shadow-register are two seperate registers; they appear only at 
the same adreses!

$FFFF8920.b [R/W]			__54__10	Track-Play-Control
							  ||  ||
							  ||  00- play 1 track
							  ||  01- play 2 tracks
							  ||  10- play 3 tracks
							  ||  11- play 4 tracks  
							  00 ---- connect track 1 with speaker
							  01 ---- connect track 2 with speaker
							  10 ---- connect track 3 with speaker
							  11 ---- connect track 4 with speaker


$FFFF8921.b [R/W]			76____10	Sound-Mode-Control 
							||	  ||
							||	  00- nute condition (on STE: 6258 Hz)	 
							||	  01- 12517 HZ
							||	  10- 25033 HZ
							||	  11- 50066 HZ
							|+------- 0:  8 Bit
							|		  1: 16 Bit
							+-------- 0: Stereo
									  1: Mono
Nice to know:							
The samplerate 6258 Hz was repleaced by a nute condition. You can use 
it to deactivate the DMA-Transfer.

$FFFF8922.w [R/-] not accessed by the XBIOS. The Falcon has no
$FFFF8924.w [R/-] Microwire-Interface!!

$FFFF8930.w [R/W]	FEDCBA9876543210	Sound-Source-Device-Prescale-Mode 
					||||||||||||||||
					|||||||||||||||| DMA-PLAY
					|||||||||||||||+ 1: Handshaking off
					|||||||||||||++  Source-Clock
					||||||||||||+	 0: if handshaking on and destination=
					||||||||||||		DSP-REC
					||||||||||||	 1: if destination<>DSP-REC
					||||||||||||		(this allows a automatic transfer from
					||||||||||||		(memory to DSP without errors.)
					||||||||||||
					||||||||||||	 DSP-XMIT
					|||||||||||+---- 1: Handshaking off
					|||||||||++----- Source-Clock
					||||||||+------- 0: Tristate, disconnect DSP from Multiplexer
					||||||||			(only if you want to use the external SSI-Port)
					||||||||		 1: connect DSP with Multiplexer
					||||||||
					||||||||		 EXT-INP
					|||||||+-------- 1: Handshaking off
					|||||++--------- Source-Clock
					||||+----------- set to zero
					||||
					||||			 A/D-Converter
					|||+------------ set to zero
					||+------------- 0: internal 25.175 MHz-Clock
					||				 1: external Clock
					++-------------- set to zero

Source-Clock can be :
					%00: internal 25.175 MHz-Clock
					%01: external Clock
					%10: internal 32 MHz-Clock, do not use it for the CODEC (A/D- and 
						  D/A-Converter).
					%11: not defined


$FFFF8932.w [R/W]	FEDCBA9876543210	Sound-Destination-Device-Matrix
					||||||||||||||||
					|||||||||||||||| EXT-OUT
					|||||||||||||||+-1: Handshaking off
					|||||||||||||++--Source-Device
					||||||||||||+----set to zero
					||||||||||||
					||||||||||||	 DAC
					|||||||||||+---- set to zero
					|||||||||++----- Source-Device
					||||||||+------- set to zero
					||||||||
					||||||||		 DMA-REC
					|||||||+-------- 1: Handshaking off
					|||||++--------- Source-Device
					||||+----------- 0: if handshaking on and source=DSP-XMIT
					||||			 1: if source<>DSP-XMIT 
					||||			 (this modus allows a automatic transfer from DSP to
					||||			  memory without errors.)
					||||
					||||			 DSP-REC
					|||+------------ 1: Handshaking off
					|++------------- Source-Device
					+--------------- 0: Tristate, disconnect DSP from Multiplexer
										(only if you want to use the external SSI-Port)
									 1: connect DSP with Multiplexer

Source-Device can be:
					%00: DMA-PLAY
					%01: DSP-XMIT (DSP send data)
					%10: EXT-INP (External Input)
					%11: A/D-Converter

$FFFF8934.b [R/W]			____3210	Prescale external Clock 
								||||	
								++++- 0: switch to STE-compatible mode
								1-15: Clock devided by 256, devided by
									   prescalevalue+1.
Documentation only allows values between 0 and 15, but the XBIOS allows 
values between 0 and 255. The upper nibble is cut by the hardware.	


$FFFF8935.b [R/W]			____3210	Prescale internal Clock (25.175 or 32 MHz)
								++++ look above! According to the Documentation
								|||| you can only use the following values for the
								|||| CODEC(A/D- and D/A-Converter) 0,1,2,3,4,5,7,9,11
								||||	   
								0000 switch to STE-compatible mode
								0001 CLK50K  49170 Hz
								0010 CLK33K  32780 Hz
								0011 CLK25K  24585 Hz
								0100 CLK20K  19668 Hz
								0101 CLK16K  16390 Hz
								0110 CLK14K  14049 Hz (invalid for CODEC)
								0111 CLK12K  12292 Hz
								1000 CLK11K  10927 Hz (invalid for CODEC)
								1001 CLK10K   9834 Hz
								1010 CLK09K   8940 Hz (invalid for CODEC)
								1011 CLK08K   8195 Hz
								1100 CLK07K   7565 Hz (invalid for CODEC)
								1101 CLK07K   7024 Hz (invalid for CODEC)
								1110 CLK06K   6556 Hz (invalid for CODEC)
								1111 CLK06K   6146 HZ (invalid for CODEC)

$FFFF8936.b [R/W]			______10	Track-Record-Control
								  ||
								  00 record 1 track
								  01 record 2 tracks
								  10 record 3 tracks
								  11 record 4 tracks

$FFFF8937.b [R/W]			______10	CODEC-Hardwareadder-Input 
								  || (ADDRIN-register)
								  || Source-input of the 16-bit-hardwareadder
								  ||
								  |+ 1: input from A/D-Converter
								  +- 1: input from Multiplexer

NOTE: The CODEC-Hardwareadder-Input connects the D/A-Converter with the 
multiplexer or the A/D-Converter. It is also possible to connect both. 
In this case the 16-bit-Hardwareadder mix the two signals.

$FFFF8938.b [R/W]			______10	A/D-Converter-Input
								  ||	(ADCINPUT-register)
								  |+ 0: input from right mic-channel
								  |  1: input from right PSG-channel
								  +- 0: input from left mic-channel
									 1: input from left PSG-channel

$FFFF8939.b [R/W]			76543210	Channel-Input-Amplifier in +1.5 dB steps 
							||||||||		   (GAIN-register)
							||||||||
							||||++++ 0-15: Gain right channel (RTGAIN) 
							++++---- 0-15: Gain left  channel (LTGAIN)


$FFFF893A.w [R/W]	____BA987654____	Channel-Output-Amplifier in -1.5 dB steps
						||||||||
						||||++++---- 0-15 Attenuation of right channel (RTATTEN)
						||||	
						++++-------- 0-15 Attenuation of left  channel(LTATTEN)
		
$FFFF893C.w [R/W]	______987654____   CODEC-Status
						   ||||||
						   |||||+--- ?
						   ||||+---- ?
						   |||+----- ?
						   ||+------ ?
						   ||
						   |+------- 1: right channel-overflow
						   +-------- 1: left channel-overflow

$FFFF893E.w [R/W]						not accessed by the XBIOS

$FFFF8941.b [R/W]			_____210	GPx-Dataportpath 
								 |||
								 +++- bidirectional Dataportpath of the GP0-
									  GP2-Pins on the DSP-Connector
									  0: Pin set to Input (read data from GPx)
									  1: Pin set to Output (write data to GPx)
									  (normally %111)

$FFFF8943.b [R/W]			_____210	GPx-Dataport
								 |||
								 +++---- Input/Output-Data-Bits of the
								 GP0-GP2-Pins on the DSP-Connector. This
								 Pins can be used for userdef. operations.

****************************************************************************
CLOCK - CHIP
****************************************************************************

$FFFF8961.b [R/W]						Register Selection
$FFFF8963.b [R/W]						Data
 

****************************************************************************
BLITTER
****************************************************************************

$FFFF8A00.w [R/W]						Halftone RAM $00
  :  :	:	  : 						:  :  :  :	 :
$FFFF8A1E.w [R/W]						Halftone RAM $0F

$FFFF8A20.w [R/W]						Source-X-Increment
$FFFF8A22.w [R/W]						Source-Y-Increment
$FFFF8A24.l [R/W]						Source-Address (24 Bit)

$FFFF8A28.w [R/W]						End-Mask 1
$FFFF8A2A.w [R/W]						End-Mask 2
$FFFF8A2C.w [R/W]						End-Mask 3

$FFFF8A2E.w [R/W]						Destination-X-Increment
$FFFF8A30.w [R/W]						Destination-Y-Increment
$FFFF8A32.l [R/W]						Destination-Address (24 Bit)

$FFFF8A36.w [R/W]						X-Count
$FFFF8A38.w [R/W]						Y-Count

$FFFF8A3A.b [R/W]						Halftone-Operation
$FFFF8A3B.b [R/W]						Logic-Operation
$FFFF8A3C.b [R/W]						Line-Number
$FFFF8A3D.b [R/W]						Skew

****************************************************************************
SERIAL - COMMUNICATIONS - CONTROLLER
****************************************************************************

$FFFF8C81.b [R/W]						Register Selection Channel A
$FFFF8C83.b [R/W]						Read / Write Data Channel A
$FFFF8C85.b [R/W]						Register Selection Channel B
$FFFF8C87.b [R/W]						Read / Write Data Channel B

****************************************************************************
JOYSTICK / LIGHTPEN - PORTS
****************************************************************************

$FFFF9200.w [R/W]	____________3210	Fire-Buttons 1-4
$FFFF9202.w [R/W]						Joysticks 1-4 
		oulroulroulroulr o= oben U=unten l=links r=rechts 0=Kontakt geschlossen
		3	2	1	0 Joystick
$FFFF9210.w [R/W]						Position Paddle 0
$FFFF9212.w [R/W]						Position Paddle 1
$FFFF9214.w [R/W]						Position Paddle 2
$FFFF9216.w [R/W]						Position Paddle 3

$FFFF9220.w [R/W]						Lightpen X-Position
$FFFF9222.w [R/W]						Lightpen Y-Position


****************************************************************************
256 COLOR - REGISTERS
****************************************************************************
		11111111111111110000000000000000
		FEDCBA9876543210FEDCBA9876543210
		rrrrrr__gggggg__________bbbbbb__ 

$FFFF9800.l [R/W]						Color $00
  :  :	:	 :							:  :  :
$FFFF9BFC.l [R/W]						Color $ff

****************************************************************************
DSP - HOST - INTERFACE
****************************************************************************

$FFFFA200.b [R/W]			76543_10	Host-Control-Register
							||||| ||
							||||| |+ 1: enable 'DSP-had-send'-IRQ
							||||| +- 1: enable 'DSP-ready to receive'-IRQ
							||||+--- Hf2-Bit, userdef. Infobit from DSP to Host
							|||+---- Hf3-Bit, userdef. Infobit from DSP to Host
							+++----- set to zero

$FFFFA201.b [R/?]						Command Vektor Register

$FFFFA202.b [R/W]			_6543_10	Host-Status-Register
							 |||| ||
							 |||| |+ 0: DSP busy
							 |||| |  1: DSP had send 
							 |||| +- 0: DSP busy
							 ||||	 1: DSP ready to receive
							 |||+--- Hf0-Bit, userdef. Infobit from Host to DSP
							 ||+---- Hf1-Bit, userdef. Infobit from Host to DSP
							 ++----- set to zero

$FFFFA203.b [R/?]						IRQ Vektor Register

$FFFFA204.l [R/W]						I/O-Data-Path (24 Bit)

$03FC-$03FF 							DSP-IRQ-vector.
This vector is used for receiving or/and sending data from/to the DSP in interrupt-mode.


HOW to send datawords to DSP in handshaking-technic:
1. step: wait until DSP ready to receive ($A202.w Bit 1 turns to 1)
2. step: write data to $A204.w-$A207.w
3. step: if you want to send once again>> goto 1. step

Example: This routine corresponds to the DSP-XBIOS:
			   LEA BUFFER(PC),A0		   ;Buffer with DSP-Words
			   MOVE.W #DSP_WORDS,D0 	   ;transfer max. 65535 DSP-Words
		 LOOP: BTST #0,$FFFFA202.W		   ;is DSP ready to receive?
			   BEQ.S LOOP
4 bytes:	   'MOVE.L (A0)+,$FFFFA204.W   ;transfer 4 bytes 
										   ;the highest byte will be ignored
										   ;by the DSP
3 bytes:	   'MOVE.B (A0)+,$FFFFA205.W   ;transfer
				MOVE.B (A0)+,$FFFFA206.W   ;3 bytes
				MOVE.B (A0)+,$FFFFA207.W   ;(1 DSP-Word has 24 Bit)
2 bytes:	   'MOVE.W (A0)+,D1 		   ;get 2 bytes
				EXT.L D1				   ;sign-extension
				MOVE.W D1,$FFFFA204.W	   ;transfer 4 bytes
1 byte: 	   'MOVE.B #0,$FFFFA205.W	   ;transfer
				MOVE.B #0,$FFFFA206.W	   ;1 byte
				MOVE.B (A0)+,$FFFFA207.W
			   DBRA D0,LOOP
 
HOW to receive datawords from DSP in handshaking-technic:
1. step: wait until DSP had send ($A202.w Bit 0 turns to 1)
1. step: wait until DSP had send ($A202.w Bit 0 turns to 1)
2. step: read data from $A204.w-$A207.w
3. step: if you want to receive once again >> goto 1. step

Example: This routine corresponds to the DSP-XBIOS
			   LEA BUFFER(PC),A0		   ;Buffer with DSP-Words
			   MOVE.W #DSP_WORDS,D0 	   ;transfer max. 65535 DSP-Words
		 LOOP: BTST #1,$FFFFA202.W		   ;had DSP send?
			   BEQ.S LOOP
4 bytes:	   'MOVE.L $FFFFA204.W,(A0)+   ;transfer 4 bytes 
										   ;the highest byte is zero
3 bytes:	   'MOVE.B $FFFFA205.W,(A0)+   ;transfer
				MOVE.B $FFFFA206.W,(A0)+   ;3 bytes
				MOVE.B $FFFFA207.W,(A0)+   ;(1 DSP-Word has 24 Bit)
2 bytes:	   'MOVE.B $FFFFA206.W,(A0)+   ;transfer		  
				MOVE.W $FFFFA207.W,(A0)+   ;2 bytes
1 byte: 	   'MOVE.B $FFFFA206.W,D1	   ;dummy-read, nobody knows why.
				MOVE.B $FFFFA207.W,(A0)+   ;transfer 1 byte
			   DBRA D0,LOOP

NOTE: it is possible to skip the 1. step. This mode increases the transfering-
rate, but the DSP-program must be able to read the data immediately, 
otherwhise the data will be overwritten by the next one. It is important 
that the DSP is ready to transfer, therefor execute the 1. step before 
transfering data! (1. step > 2. step > 2. step > 2. step ......until end)


HOW to send datawords to DSP in interrupt-technic:
	  1. step: IRQ-Instalation in special order:
	   1.: write the IRQ-program-address in the DSP-IRQ-vector
	   2.: write register $A203.w with $FF
	   3.: set bit 1 of Host-Control-Register
		now the DSP-IRQ is installed and enabled!
	  2. step: the style of the IRQ-vector-routine:
	   1.: read data from $A204.w-$A207.w
	   2.: end the IRQ-routine with a RTE
	  3. step: you have two possibilities to stop the IRQ-transfer:
	   1.: you clear bit 1 in the main program
	   2.: you clear bit 1 in the IRQ-program 

HOW to receive datawords fron DSP in interrupt-technic:
	  1. step: IRQ-Instalation in special order:
	   1.: write the IRQ-program-address in the DSP-IRQ-vector
	   2.: write register $A203.w with $FF
	   3.: set bit 0 of Host-Control-Register
		now the DSP-IRQ is installed and enabled!
	  2. step: the style of the IRQ-vector-routine:
	   1.: write data to $A204.w-$A207.w
	   2.: end the IRQ-routine with a RTE
	  3. step: you have two possibilities to stop the IRQ-transfer:
	   1.: you clear bit 0 in the main program
	   2.: you clear bit 0 in the IRQ-program 
			   
NOTE: You have only one exception for sending and receiving data. But it is 
possible to send and receive data simultanously. In the IRQ-program you 
have to test bit 0/1 of the Host-Status-Register to get information about 
the transfering direction!



****************************************************************************
MULTI - FUNCTION - PERIPHERAL MC 68901
****************************************************************************

$FFFFFA01.b [R/W]						GPIP-Data
$FFFFFA03.b [R/W]						Active-Edge
$FFFFFA05.b [R/W]						Data-Direction
$FFFFFA07.b [R/W]						Interrupt-Enable A
$FFFFFA09.b [R/W]						Interrupt-Enable B
$FFFFFA0B.b [R/W]						Interrupt-Pending A
$FFFFFA0D.b [R/W]						Interrupt-Pending B
$FFFFFA0F.b [R/W]						Interrupt-In-Service A
$FFFFFA11.b [R/W]						Interrupt-In-Service B
$FFFFFA13.b [R/W]						Interrupt-Mask A
$FFFFFA15.b [R/W]						Interrupt-Mask B
$FFFFFA17.b [R/W]						Interrupt-Vektor
$FFFFFA19.b [R/W]						Timer-A-Control
$FFFFFA1B.b [R/W]						Timer-B-Control
$FFFFFA1D.b [R/W]						Timer-C+D-Control
$FFFFFA1F.b [R/W]						Timer-A-Data
$FFFFFA21.b [R/W]						Timer-B-Data
$FFFFFA23.b [R/W]						Timer-C-Data
$FFFFFA25.b [R/W]						Timer-D-Data
$FFFFFA27.b [R/W]						Synchronous-Character
$FFFFFA29.b [R/W]						USART-Control
$FFFFFA2B.b [R/W]						Receiver-Status
$FFFFFA2D.b [R/W]						Transmitter-Status
$FFFFFA2F.b [R/W]						USART-Data
 
****************************************************************************
KEYBOARD / MIDI - ACIAS 6850
****************************************************************************

$FFFFFC00.b [R/-]						Keyboard-Status
			[-/W]						Keyboard-Control
$FFFFFC02.b [R/-]						Keyboard-Receive
			[-/W]						Keyboard-Send

$FFFFFC04.b [R/-]						Midi-Status
			[-/W]						Midi-Control
$FFFFFC06.b [R/-]						Midi-Receive
			[-/W]						Midi-Send

****************************************************************************
??????
****************************************************************************

$FFFFFF82.w [R/-]						new

******************************** END OF FILE *******************************

