Timing Report

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Design Name TurboFreezer
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sun Nov 18 14:43:56 2012
Created By Timing Report Generator: version M.81d
Copyright Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 29.700 ns.
Max. Clock Frequency (fSYSTEM) 33.670 MHz.
Limited by Cycle Time for phi2short
Clock to Setup (tCYC) 29.700 ns.
Pad to Pad Delay (tPD) 74.800 ns.
Setup to Clock at the Pad (tSU) 53.600 ns.
Clock Pad to Output Pad Delay (tCO) 104.700 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_phi2short 560.0 29.7 166 0
TS_phi2 560.0 29.7 61 0


Constraint: TS_phi2short

Description: PERIOD:phi2short:560.000nS:LOW:280.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
use_pia/pia_crb2.Q to use_pia/pia_portb<2>.D 560.000 29.700 530.300
use_pia/pia_crb2.Q to use_pia/pia_portb<3>.D 560.000 29.700 530.300
use_pia/pia_crb2.Q to use_pia/pia_portb<4>.D 560.000 29.700 530.300


Constraint: TS_phi2

Description: PERIOD:phi2:560.000nS:LOW:280.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
reset_n_sync<1>.Q to use_cartemu/cfg_sram_bank<0>.D 560.000 29.700 530.300
reset_n_sync<1>.Q to use_cartemu/cfg_sram_bank<1>.D 560.000 29.700 530.300
reset_n_sync<1>.Q to use_cartemu/cfg_sram_bank<2>.D 560.000 29.700 530.300



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
phi2 64.516 Limited by Cycle Time for phi2
phi2short 33.670 Limited by Cycle Time for phi2short

Setup/Hold Times for Clocks

Setup/Hold Times for Clock phi2
Source Pad Setup to clk (edge) Hold to clk (edge)
activate_n_in 12.000 0.000
reset_n_in 12.000 0.000

Setup/Hold Times for Clock phi2short
Source Pad Setup to clk (edge) Hold to clk (edge)
a<0> 26.200 0.000
a<10> 40.400 0.000
a<11> 52.600 0.000
a<12> 52.600 0.000
a<13> 52.600 0.000
a<14> 52.600 0.000
a<15> 52.600 0.000
a<1> 26.200 0.000
a<2> 26.200 0.000
a<3> 26.200 0.000
a<4> 53.600 0.000
a<5> 53.600 0.000
a<6> 53.600 0.000
a<7> 52.600 0.000
a<8> 40.400 0.000
a<9> 40.400 0.000
cartemu_enable_n 40.400 0.000
d<0> 13.400 0.000
d<1> 12.000 0.000
d<2> 13.000 0.000
d<3> 12.000 0.000
d<4> 12.000 0.000
d<5> 12.000 0.000
d<6> 12.000 0.000
d<7> 12.000 0.000
flash_we_n 40.400 0.000
rw 26.200 0.000


Clock to Pad Timing

Clock phi2 to Pad
Destination Pad Clock (edge) to Pad
ram_rom_a<13> 63.100
ram_rom_a<14> 63.100
ram_rom_a<15> 63.100
ram_rom_a<16> 63.100
d<0> 55.100
d<1> 55.100
d<2> 55.100
d<3> 55.100
d<4> 55.100
d<5> 55.100
d<6> 55.100
d<7> 55.100
refresh 55.100
ram0_ce 50.900
ram_a<4> 50.900
ram_a<5> 50.900
ram_rom_a<12> 50.900
ram_rom_a<17> 50.900
ram_rom_a<18> 50.900
rom0_ce 50.900
rom1_ce 50.900
ram1_ce 49.900
ram_a<6> 49.900
ram_a<7> 49.900

Clock phi2short to Pad
Destination Pad Clock (edge) to Pad
ram0_ce 104.700
ram_rom_a<12> 104.700
ram_rom_a<13> 104.700
rom0_ce 104.700
rom1_ce 104.700
ram1_ce 103.700
ram_a<4> 103.700
ram_a<5> 103.700
ram_a<6> 103.700
ram_a<7> 103.700
ram_rom_a<14> 103.700
ram_rom_a<15> 103.700
ram_rom_a<16> 103.700
ram_rom_a<17> 103.700
ram_rom_a<18> 103.700
refresh 94.700
d<0> 67.300
d<1> 67.300
d<2> 67.300
d<3> 67.300
d<4> 67.300
d<5> 67.300
d<6> 67.300
d<7> 67.300


Clock to Setup Times for Clocks

Clock to Setup for clock phi2
Source Destination Delay
activate_n_sync<0>.Q activate_n_sync<1>.D 15.500
reset_n_sync<0>.Q reset_n_sync<1>.D 15.500
reset_n_sync<1>.Q reset_n_sync<2>.D 15.500
reset_n_sync<2>.Q reset_n_sync<3>.D 15.500
powerup_n.Q powerup_n.CE 10.000
reset_n_sync<2>.Q powerup_n.CE 10.000
reset_n_sync<3>.Q powerup_n.CE 10.000

Clock to Setup for clock phi2short
Source Destination Delay
use_pia/pia_crb2.Q use_pia/pia_portb<2>.D 29.700
use_pia/pia_crb2.Q use_pia/pia_portb<3>.D 29.700
use_pia/pia_crb2.Q use_pia/pia_portb<4>.D 29.700
use_pia/pia_crb2.Q use_pia/pia_portb<5>.D 29.700
use_pia/pia_crb2.Q use_pia/pia_portb<6>.D 29.700
use_pia/pia_crb2.Q use_pia/pia_portb<7>.D 29.700
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<0>.D 28.700
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<1>.D 28.700
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<2>.D 28.700
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<3>.D 28.700
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<4>.D 28.700
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<5>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<0>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<1>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<2>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<3>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<4>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<5>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/oss_bank<0>.D 28.700
use_cartemu/cfg_mode<1>.Q use_cartemu/oss_bank<1>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<0>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<1>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<2>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<3>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<4>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<5>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/oss_bank<0>.D 28.700
use_cartemu/cfg_mode<2>.Q use_cartemu/oss_bank<1>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_bank<0>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_bank<1>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_bank<2>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_bank<3>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_bank<4>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_bank<5>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_ctl<0>.D 28.700
use_cartemu/cfg_usdx<0>.Q use_cartemu/usdx_ctl<1>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_bank<0>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_bank<1>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_bank<2>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_bank<3>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_bank<4>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_bank<5>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_ctl<0>.D 28.700
use_cartemu/cfg_usdx<1>.Q use_cartemu/usdx_ctl<1>.D 28.700
use_pia/pia_crb2.Q use_pia/pia_ddrb<2>.D 28.700
use_pia/pia_crb2.Q use_pia/pia_ddrb<3>.D 28.700
use_pia/pia_crb2.Q use_pia/pia_ddrb<4>.D 28.700
use_pia/pia_crb2.Q use_pia/pia_ddrb<5>.D 28.700
use_pia/pia_crb2.Q use_pia/pia_ddrb<6>.D 28.700
use_pia/pia_crb2.Q use_pia/pia_ddrb<7>.D 28.700
use_cartemu/cfg_enable.Q use_cartemu/cfg_enable.D 16.900
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_enable.D 16.900
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_enable.D 16.900
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_write_enable.D 16.500
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_enable.D 16.500
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_write_enable.D 16.500
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_write_enable.D 16.500
use_cartemu/cfg_write_enable.Q use_cartemu/cfg_write_enable.D 16.500
use_cartemu/cfg_bank<0>.Q use_cartemu/cfg_bank<0>.D 15.500
use_cartemu/cfg_bank<1>.Q use_cartemu/cfg_bank<1>.D 15.500
use_cartemu/cfg_bank<2>.Q use_cartemu/cfg_bank<2>.D 15.500
use_cartemu/cfg_bank<3>.Q use_cartemu/cfg_bank<3>.D 15.500
use_cartemu/cfg_bank<4>.Q use_cartemu/cfg_bank<4>.D 15.500
use_cartemu/cfg_bank<5>.Q use_cartemu/cfg_bank<5>.D 15.500
use_cartemu/cfg_bank<6>.Q use_cartemu/cfg_bank<6>.D 15.500
use_cartemu/cfg_menu.Q use_cartemu/cfg_menu.D 15.500
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_bank<6>.D 15.500
use_cartemu/cfg_mode<0>.Q use_cartemu/cfg_mode<0>.D 15.500
use_cartemu/cfg_mode<0>.Q use_cartemu/oss_bank<0>.D 15.500
use_cartemu/cfg_mode<0>.Q use_cartemu/oss_bank<1>.D 15.500
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_bank<6>.D 15.500
use_cartemu/cfg_mode<1>.Q use_cartemu/cfg_mode<1>.D 15.500
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_bank<6>.D 15.500
use_cartemu/cfg_mode<2>.Q use_cartemu/cfg_mode<2>.D 15.500
use_cartemu/cfg_source_ram.Q use_cartemu/cfg_source_ram.D 15.500
use_cartemu/cfg_sram_bank<0>.Q use_cartemu/cfg_sram_bank<0>.D 15.500
use_cartemu/cfg_sram_bank<1>.Q use_cartemu/cfg_sram_bank<1>.D 15.500
use_cartemu/cfg_sram_bank<2>.Q use_cartemu/cfg_sram_bank<2>.D 15.500
use_cartemu/cfg_sram_bank<3>.Q use_cartemu/cfg_sram_bank<3>.D 15.500
use_cartemu/cfg_sram_bank<4>.Q use_cartemu/cfg_sram_bank<4>.D 15.500
use_cartemu/cfg_sram_bank<5>.Q use_cartemu/cfg_sram_bank<5>.D 15.500
use_cartemu/cfg_sram_enable.Q use_cartemu/cfg_sram_enable.D 15.500
use_cartemu/cfg_usdx<0>.Q use_cartemu/cfg_usdx<0>.D 15.500
use_cartemu/cfg_usdx<1>.Q use_cartemu/cfg_usdx<1>.D 15.500
use_cartemu/oss_bank<0>.Q use_cartemu/oss_bank<0>.D 15.500
use_cartemu/oss_bank<1>.Q use_cartemu/oss_bank<1>.D 15.500
use_cartemu/usdx_bank<0>.Q use_cartemu/usdx_bank<0>.D 15.500
use_cartemu/usdx_bank<1>.Q use_cartemu/usdx_bank<1>.D 15.500
use_cartemu/usdx_bank<2>.Q use_cartemu/usdx_bank<2>.D 15.500
use_cartemu/usdx_bank<3>.Q use_cartemu/usdx_bank<3>.D 15.500
use_cartemu/usdx_bank<4>.Q use_cartemu/usdx_bank<4>.D 15.500
use_cartemu/usdx_bank<5>.Q use_cartemu/usdx_bank<5>.D 15.500
use_cartemu/usdx_ctl<0>.Q use_cartemu/usdx_ctl<0>.D 15.500
use_cartemu/usdx_ctl<1>.Q use_cartemu/usdx_ctl<1>.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/next_state_FSM_FFd1.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/next_state_FSM_FFd2.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/next_state_FSM_FFd3.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/ram_bank_0.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/ram_bank_1.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/ram_bank_2.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/ram_bank_3.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/ram_bank_4.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/rom_bank_0.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/rom_bank_1.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/rom_bank_2.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/rom_bank_3.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/rom_bank_4.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/rom_bank_5.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/use_status_as_ram_address<0>.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/next_state_FSM_FFd1.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/next_state_FSM_FFd2.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/next_state_FSM_FFd3.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/ram_bank_0.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/ram_bank_1.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/ram_bank_2.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/ram_bank_3.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/ram_bank_4.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/rom_bank_0.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/rom_bank_1.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/rom_bank_2.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/rom_bank_3.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/rom_bank_4.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/rom_bank_5.D 15.500
use_freezer/next_state_FSM_FFd2.Q use_freezer/use_status_as_ram_address<0>.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/next_state_FSM_FFd2.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/next_state_FSM_FFd3.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/ram_bank_0.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/ram_bank_1.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/ram_bank_2.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/ram_bank_3.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/ram_bank_4.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/rom_bank_0.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/rom_bank_1.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/rom_bank_2.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/rom_bank_3.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/rom_bank_4.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/rom_bank_5.D 15.500
use_freezer/next_state_FSM_FFd3.Q use_freezer/use_status_as_ram_address<0>.D 15.500
use_freezer/ram_bank_0.Q use_freezer/ram_bank_0.D 15.500
use_freezer/ram_bank_1.Q use_freezer/ram_bank_1.D 15.500
use_freezer/ram_bank_2.Q use_freezer/ram_bank_2.D 15.500
use_freezer/ram_bank_3.Q use_freezer/ram_bank_3.D 15.500
use_freezer/ram_bank_4.Q use_freezer/ram_bank_4.D 15.500
use_freezer/rom_bank_0.Q use_freezer/rom_bank_0.D 15.500
use_freezer/rom_bank_1.Q use_freezer/rom_bank_1.D 15.500
use_freezer/rom_bank_2.Q use_freezer/rom_bank_2.D 15.500
use_freezer/rom_bank_3.Q use_freezer/rom_bank_3.D 15.500
use_freezer/rom_bank_4.Q use_freezer/rom_bank_4.D 15.500
use_freezer/rom_bank_5.Q use_freezer/rom_bank_5.D 15.500
use_freezer/use_status_as_ram_address<0>.Q use_freezer/use_status_as_ram_address<0>.D 15.500
use_pia/pia_crb2.Q use_pia/pia_crb2.D 15.500
use_pia/pia_ddrb<2>.Q use_pia/pia_ddrb<2>.D 15.500
use_pia/pia_ddrb<3>.Q use_pia/pia_ddrb<3>.D 15.500
use_pia/pia_ddrb<4>.Q use_pia/pia_ddrb<4>.D 15.500
use_pia/pia_ddrb<5>.Q use_pia/pia_ddrb<5>.D 15.500
use_pia/pia_ddrb<6>.Q use_pia/pia_ddrb<6>.D 15.500
use_pia/pia_ddrb<7>.Q use_pia/pia_ddrb<7>.D 15.500
use_pia/pia_portb<2>.Q use_pia/pia_portb<2>.D 15.500
use_pia/pia_portb<3>.Q use_pia/pia_portb<3>.D 15.500
use_pia/pia_portb<4>.Q use_pia/pia_portb<4>.D 15.500
use_pia/pia_portb<5>.Q use_pia/pia_portb<5>.D 15.500
use_pia/pia_portb<6>.Q use_pia/pia_portb<6>.D 15.500
use_pia/pia_portb<7>.Q use_pia/pia_portb<7>.D 15.500
use_freezer/next_state_FSM_FFd1.Q use_freezer/vector_a2.CE 10.000
use_freezer/next_state_FSM_FFd2.Q use_freezer/vector_a2.CE 10.000
use_freezer/next_state_FSM_FFd3.Q use_freezer/vector_a2.CE 10.000


Pad to Pad List

Source Pad Destination Pad Delay
a<13> ram0_ce 74.800
a<13> ram_rom_a<12> 74.800
a<13> ram_rom_a<13> 74.800
a<13> rom0_ce 74.800
a<13> rom1_ce 74.800
a<14> ram0_ce 74.800
a<14> ram_rom_a<12> 74.800
a<14> ram_rom_a<13> 74.800
a<14> rom0_ce 74.800
a<14> rom1_ce 74.800
a<15> ram0_ce 74.800
a<15> ram_rom_a<12> 74.800
a<15> ram_rom_a<13> 74.800
a<15> rom0_ce 74.800
a<15> rom1_ce 74.800
a<13> ram1_ce 73.800
a<13> ram_a<4> 73.800
a<13> ram_a<5> 73.800
a<13> ram_a<6> 73.800
a<13> ram_a<7> 73.800
a<13> ram_rom_a<14> 73.800
a<13> ram_rom_a<15> 73.800
a<13> ram_rom_a<16> 73.800
a<13> ram_rom_a<17> 73.800
a<13> ram_rom_a<18> 73.800
a<14> ram1_ce 73.800
a<14> ram_a<4> 73.800
a<14> ram_a<5> 73.800
a<14> ram_a<6> 73.800
a<14> ram_a<7> 73.800
a<14> ram_rom_a<14> 73.800
a<14> ram_rom_a<15> 73.800
a<14> ram_rom_a<16> 73.800
a<14> ram_rom_a<17> 73.800
a<14> ram_rom_a<18> 73.800
a<15> ram1_ce 73.800
a<15> ram_a<4> 73.800
a<15> ram_a<5> 73.800
a<15> ram_a<6> 73.800
a<15> ram_a<7> 73.800
a<15> ram_rom_a<14> 73.800
a<15> ram_rom_a<15> 73.800
a<15> ram_rom_a<16> 73.800
a<15> ram_rom_a<17> 73.800
a<15> ram_rom_a<18> 73.800
a<13> refresh 64.800
a<14> refresh 64.800
a<15> refresh 64.800
a<0> ram_rom_a<13> 59.600
a<0> ram_rom_a<14> 59.600
a<0> ram_rom_a<15> 59.600
a<0> ram_rom_a<16> 59.600
a<10> ram_rom_a<13> 59.600
a<10> ram_rom_a<14> 59.600
a<10> ram_rom_a<15> 59.600
a<10> ram_rom_a<16> 59.600
a<11> ram_rom_a<13> 59.600
a<11> ram_rom_a<14> 59.600
a<11> ram_rom_a<15> 59.600
a<11> ram_rom_a<16> 59.600
a<12> ram_rom_a<13> 59.600
a<12> ram_rom_a<14> 59.600
a<12> ram_rom_a<15> 59.600
a<12> ram_rom_a<16> 59.600
a<3> ram_rom_a<13> 59.600
a<3> ram_rom_a<14> 59.600
a<3> ram_rom_a<15> 59.600
a<3> ram_rom_a<16> 59.600
a<4> ram_rom_a<13> 59.600
a<4> ram_rom_a<14> 59.600
a<4> ram_rom_a<15> 59.600
a<4> ram_rom_a<16> 59.600
a<5> ram_rom_a<13> 59.600
a<5> ram_rom_a<14> 59.600
a<5> ram_rom_a<15> 59.600
a<5> ram_rom_a<16> 59.600
a<6> ram_rom_a<13> 59.600
a<6> ram_rom_a<14> 59.600
a<6> ram_rom_a<15> 59.600
a<6> ram_rom_a<16> 59.600
a<7> ram_rom_a<13> 59.600
a<7> ram_rom_a<14> 59.600
a<7> ram_rom_a<15> 59.600
a<7> ram_rom_a<16> 59.600
a<8> ram_rom_a<13> 59.600
a<8> ram_rom_a<14> 59.600
a<8> ram_rom_a<15> 59.600
a<8> ram_rom_a<16> 59.600
a<9> ram_rom_a<13> 59.600
a<9> ram_rom_a<14> 59.600
a<9> ram_rom_a<15> 59.600
a<9> ram_rom_a<16> 59.600
rw ram_rom_a<13> 59.600
rw ram_rom_a<14> 59.600
rw ram_rom_a<15> 59.600
rw ram_rom_a<16> 59.600
a<10> refresh 52.600
a<11> refresh 52.600
a<12> refresh 52.600
a<4> refresh 52.600
a<5> refresh 52.600
a<6> refresh 52.600
a<8> refresh 52.600
a<9> refresh 52.600
cartemu_enable_n refresh 52.600
flash_we_n refresh 52.600
a<0> d<0> 51.600
a<0> d<1> 51.600
a<0> d<2> 51.600
a<0> d<3> 51.600
a<0> d<4> 51.600
a<0> d<5> 51.600
a<0> d<6> 51.600
a<0> d<7> 51.600
a<0> refresh 51.600
a<10> d<0> 51.600
a<10> d<1> 51.600
a<10> d<2> 51.600
a<10> d<3> 51.600
a<10> d<4> 51.600
a<10> d<5> 51.600
a<10> d<6> 51.600
a<10> d<7> 51.600
a<11> d<0> 51.600
a<11> d<1> 51.600
a<11> d<2> 51.600
a<11> d<3> 51.600
a<11> d<4> 51.600
a<11> d<5> 51.600
a<11> d<6> 51.600
a<11> d<7> 51.600
a<12> d<0> 51.600
a<12> d<1> 51.600
a<12> d<2> 51.600
a<12> d<3> 51.600
a<12> d<4> 51.600
a<12> d<5> 51.600
a<12> d<6> 51.600
a<12> d<7> 51.600
a<13> d<0> 51.600
a<13> d<1> 51.600
a<13> d<2> 51.600
a<13> d<3> 51.600
a<13> d<4> 51.600
a<13> d<5> 51.600
a<13> d<6> 51.600
a<13> d<7> 51.600
a<14> d<0> 51.600
a<14> d<1> 51.600
a<14> d<2> 51.600
a<14> d<3> 51.600
a<14> d<4> 51.600
a<14> d<5> 51.600
a<14> d<6> 51.600
a<14> d<7> 51.600
a<15> d<0> 51.600
a<15> d<1> 51.600
a<15> d<2> 51.600
a<15> d<3> 51.600
a<15> d<4> 51.600
a<15> d<5> 51.600
a<15> d<6> 51.600
a<15> d<7> 51.600
a<3> d<0> 51.600
a<3> d<1> 51.600
a<3> d<2> 51.600
a<3> d<3> 51.600
a<3> d<4> 51.600
a<3> d<5> 51.600
a<3> d<6> 51.600
a<3> d<7> 51.600
a<3> refresh 51.600
a<4> d<0> 51.600
a<4> d<1> 51.600
a<4> d<2> 51.600
a<4> d<3> 51.600
a<4> d<4> 51.600
a<4> d<5> 51.600
a<4> d<6> 51.600
a<4> d<7> 51.600
a<5> d<0> 51.600
a<5> d<1> 51.600
a<5> d<2> 51.600
a<5> d<3> 51.600
a<5> d<4> 51.600
a<5> d<5> 51.600
a<5> d<6> 51.600
a<5> d<7> 51.600
a<6> d<0> 51.600
a<6> d<1> 51.600
a<6> d<2> 51.600
a<6> d<3> 51.600
a<6> d<4> 51.600
a<6> d<5> 51.600
a<6> d<6> 51.600
a<6> d<7> 51.600
a<7> d<0> 51.600
a<7> d<1> 51.600
a<7> d<2> 51.600
a<7> d<3> 51.600
a<7> d<4> 51.600
a<7> d<5> 51.600
a<7> d<6> 51.600
a<7> d<7> 51.600
a<7> refresh 51.600
a<8> d<0> 51.600
a<8> d<1> 51.600
a<8> d<2> 51.600
a<8> d<3> 51.600
a<8> d<4> 51.600
a<8> d<5> 51.600
a<8> d<6> 51.600
a<8> d<7> 51.600
a<9> d<0> 51.600
a<9> d<1> 51.600
a<9> d<2> 51.600
a<9> d<3> 51.600
a<9> d<4> 51.600
a<9> d<5> 51.600
a<9> d<6> 51.600
a<9> d<7> 51.600
rw d<0> 51.600
rw d<1> 51.600
rw d<2> 51.600
rw d<3> 51.600
rw d<4> 51.600
rw d<5> 51.600
rw d<6> 51.600
rw d<7> 51.600
rw refresh 51.600
a<1> refresh 50.600
a<2> refresh 50.600
a<0> ram0_ce 47.400
a<0> ram_a<4> 47.400
a<0> ram_a<5> 47.400
a<0> ram_rom_a<12> 47.400
a<0> ram_rom_a<17> 47.400
a<0> ram_rom_a<18> 47.400
a<0> rom0_ce 47.400
a<0> rom1_ce 47.400
a<10> ram0_ce 47.400
a<10> ram_a<4> 47.400
a<10> ram_a<5> 47.400
a<10> ram_rom_a<12> 47.400
a<10> ram_rom_a<17> 47.400
a<10> ram_rom_a<18> 47.400
a<10> rom0_ce 47.400
a<10> rom1_ce 47.400
a<11> ram0_ce 47.400
a<11> ram_a<4> 47.400
a<11> ram_a<5> 47.400
a<11> ram_rom_a<12> 47.400
a<11> ram_rom_a<17> 47.400
a<11> ram_rom_a<18> 47.400
a<11> rom0_ce 47.400
a<11> rom1_ce 47.400
a<12> ram0_ce 47.400
a<12> ram_a<4> 47.400
a<12> ram_a<5> 47.400
a<12> ram_rom_a<12> 47.400
a<12> ram_rom_a<17> 47.400
a<12> ram_rom_a<18> 47.400
a<12> rom0_ce 47.400
a<12> rom1_ce 47.400
a<3> ram0_ce 47.400
a<3> ram_a<4> 47.400
a<3> ram_a<5> 47.400
a<3> ram_rom_a<12> 47.400
a<3> ram_rom_a<17> 47.400
a<3> ram_rom_a<18> 47.400
a<3> rom0_ce 47.400
a<3> rom1_ce 47.400
a<4> ram0_ce 47.400
a<4> ram_a<4> 47.400
a<4> ram_a<5> 47.400
a<4> ram_rom_a<12> 47.400
a<4> ram_rom_a<17> 47.400
a<4> ram_rom_a<18> 47.400
a<4> rom0_ce 47.400
a<4> rom1_ce 47.400
a<5> ram0_ce 47.400
a<5> ram_a<4> 47.400
a<5> ram_a<5> 47.400
a<5> ram_rom_a<12> 47.400
a<5> ram_rom_a<17> 47.400
a<5> ram_rom_a<18> 47.400
a<5> rom0_ce 47.400
a<5> rom1_ce 47.400
a<6> ram0_ce 47.400
a<6> ram_a<4> 47.400
a<6> ram_a<5> 47.400
a<6> ram_rom_a<12> 47.400
a<6> ram_rom_a<17> 47.400
a<6> ram_rom_a<18> 47.400
a<6> rom0_ce 47.400
a<6> rom1_ce 47.400
a<7> ram0_ce 47.400
a<7> ram_a<4> 47.400
a<7> ram_a<5> 47.400
a<7> ram_rom_a<12> 47.400
a<7> ram_rom_a<17> 47.400
a<7> ram_rom_a<18> 47.400
a<7> rom0_ce 47.400
a<7> rom1_ce 47.400
a<8> ram0_ce 47.400
a<8> ram_a<4> 47.400
a<8> ram_a<5> 47.400
a<8> ram_rom_a<12> 47.400
a<8> ram_rom_a<17> 47.400
a<8> ram_rom_a<18> 47.400
a<8> rom0_ce 47.400
a<8> rom1_ce 47.400
a<9> ram0_ce 47.400
a<9> ram_a<4> 47.400
a<9> ram_a<5> 47.400
a<9> ram_rom_a<12> 47.400
a<9> ram_rom_a<17> 47.400
a<9> ram_rom_a<18> 47.400
a<9> rom0_ce 47.400
a<9> rom1_ce 47.400
rw ram0_ce 47.400
rw ram_a<4> 47.400
rw ram_a<5> 47.400
rw ram_rom_a<12> 47.400
rw ram_rom_a<17> 47.400
rw ram_rom_a<18> 47.400
rw rom0_ce 47.400
rw rom1_ce 47.400
a<0> ram1_ce 46.400
a<0> ram_a<6> 46.400
a<0> ram_a<7> 46.400
a<10> ram1_ce 46.400
a<10> ram_a<6> 46.400
a<10> ram_a<7> 46.400
a<11> ram1_ce 46.400
a<11> ram_a<6> 46.400
a<11> ram_a<7> 46.400
a<12> ram1_ce 46.400
a<12> ram_a<6> 46.400
a<12> ram_a<7> 46.400
a<3> ram1_ce 46.400
a<3> ram_a<6> 46.400
a<3> ram_a<7> 46.400
a<4> ram1_ce 46.400
a<4> ram_a<6> 46.400
a<4> ram_a<7> 46.400
a<5> ram1_ce 46.400
a<5> ram_a<6> 46.400
a<5> ram_a<7> 46.400
a<6> ram1_ce 46.400
a<6> ram_a<6> 46.400
a<6> ram_a<7> 46.400
a<7> ram1_ce 46.400
a<7> ram_a<6> 46.400
a<7> ram_a<7> 46.400
a<8> ram1_ce 46.400
a<8> ram_a<6> 46.400
a<8> ram_a<7> 46.400
a<9> ram1_ce 46.400
a<9> ram_a<6> 46.400
a<9> ram_a<7> 46.400
rw ram1_ce 46.400
rw ram_a<6> 46.400
rw ram_a<7> 46.400
cartemu_enable_n d<0> 39.400
cartemu_enable_n d<1> 39.400
cartemu_enable_n d<2> 39.400
cartemu_enable_n d<3> 39.400
cartemu_enable_n d<4> 39.400
cartemu_enable_n d<5> 39.400
cartemu_enable_n d<6> 39.400
cartemu_enable_n d<7> 39.400
flash_we_n d<0> 39.400
flash_we_n d<1> 39.400
flash_we_n d<2> 39.400
flash_we_n d<3> 39.400
flash_we_n d<4> 39.400
flash_we_n d<5> 39.400
flash_we_n d<6> 39.400
flash_we_n d<7> 39.400
a<1> d<0> 37.400
a<1> d<1> 37.400
a<1> d<2> 37.400
a<1> d<3> 37.400
a<1> d<4> 37.400
a<1> d<5> 37.400
a<1> d<6> 37.400
a<1> d<7> 37.400
a<2> d<0> 37.400
a<2> d<1> 37.400
a<2> d<2> 37.400
a<2> d<3> 37.400
a<2> d<4> 37.400
a<2> d<5> 37.400
a<2> d<6> 37.400
a<2> d<7> 37.400
oldos_n refresh 37.400
ramdisk_enable_n refresh 37.400
flash_we_n ram0_ce 34.200
flash_we_n ram_rom_a<12> 34.200
flash_we_n ram_rom_a<13> 34.200
flash_we_n rom0_ce 34.200
flash_we_n rom1_ce 34.200
ramdisk_enable_n ram0_ce 34.200
ramdisk_enable_n ram_rom_a<14> 34.200
ramdisk_enable_n ram_rom_a<16> 34.200
ramdisk_enable_n rom0_ce 34.200
flash_we_n ram1_ce 33.200
flash_we_n ram_a<4> 33.200
flash_we_n ram_a<5> 33.200
flash_we_n ram_a<6> 33.200
flash_we_n ram_a<7> 33.200
flash_we_n ram_rom_a<14> 33.200
flash_we_n ram_rom_a<15> 33.200
flash_we_n ram_rom_a<16> 33.200
flash_we_n ram_rom_a<17> 33.200
flash_we_n ram_rom_a<18> 33.200
oldos_n ram_rom_a<13> 33.200
oldos_n ram_rom_a<14> 33.200
oldos_n ram_rom_a<15> 33.200
oldos_n ram_rom_a<16> 33.200
ramdisk_enable_n ram1_ce 33.200
ramdisk_enable_n ram_a<4> 33.200
ramdisk_enable_n ram_a<5> 33.200
ramdisk_enable_n ram_a<6> 33.200
ramdisk_enable_n ram_a<7> 33.200
ramdisk_enable_n ram_rom_a<12> 33.200
ramdisk_enable_n ram_rom_a<13> 33.200
ramdisk_enable_n ram_rom_a<15> 33.200
ramdisk_enable_n ram_rom_a<17> 33.200
ramdisk_enable_n ram_rom_a<18> 33.200
ramdisk_enable_n rom1_ce 33.200
phi2 d<0> 25.200
phi2 d<1> 25.200
phi2 d<2> 25.200
phi2 d<3> 25.200
phi2 d<4> 25.200
phi2 d<5> 25.200
phi2 d<6> 25.200
phi2 d<7> 25.200
dualpokey_n ram_a<4> 21.000
oldos_n ram0_ce 21.000
oldos_n ram_a<4> 21.000
oldos_n ram_a<5> 21.000
oldos_n ram_rom_a<12> 21.000
oldos_n ram_rom_a<17> 21.000
oldos_n ram_rom_a<18> 21.000
oldos_n rom0_ce 21.000
oldos_n rom1_ce 21.000
phi2 ram0_ce 21.000
phi2 rom0_ce 21.000
phi2 rom1_ce 21.000
phi2short ram_rom_we 21.000
rw ram_rom_we 21.000
dualpokey_n ram_a<5> 20.000
oldos_n ram1_ce 20.000
oldos_n ram_a<6> 20.000
oldos_n ram_a<7> 20.000
phi2 ram1_ce 20.000
phi2 ram_rom_oe 20.000
rw ram_rom_oe 20.000


Number of paths analyzed: 227
Number of Timing errors: 0
Analysis Completed: Sun Nov 18 14:43:56 2012