 .OPT NO LIST›; SAVE #D1:MACROS.M65›;›; The following force MAC/65 to›; use absolute addressing with›; zero page addresses to match›; the original. It is considered›; these are more readable than›; the actual .BYTE and .WORD›; definitions.›;›; Produces AND $00xx› .MACRO AAND› .BYTE $2D› .WORD %1› .ENDM›;›; Produces EOR $00xx› .MACRO AEOR› .BYTE $4D› .WORD %1› .ENDM›;›; Produces LDA $00xx› .MACRO ALDA› .BYTE $AD› .WORD %1› .ENDM›;›; Produces LDX $00xx› .MACRO ALDX› .BYTE $AE› .WORD %1› .ENDM›;›; Produces STA $00xx› .MACRO ASTA› .BYTE $8D› .WORD %1› .ENDM›;›; Produces STX $00xx› .MACRO ASTX› .BYTE $8E› .WORD %1› .ENDM›;›; Readability. These replace›; the phony BIT opcodes that›; skip one or two bytes›;› .MACRO SKIPB› .BYTE $24› .ENDM›;› .MACRO SKIPW› .BYTE $2C› .ENDM›;›; Display list›;›; Insert 1-8 blank scan lines›; usage BLANK [n]›;› .MACRO BLANK› .IF %0=0› .BYTE 0› .ELSE› .BYTE [%1-1]*$10› .ENDIF› .ENDM›;›; Load memory scan, display mode 2›; usage LMS Address›;› .MACRO LMS› .BYTE $42› .WORD %1› .ENDM›;›; jump and wait for vertical blank›; usage JVB Address›;› .MACRO JVB› .BYTE $41› .WORD %1› .ENDM›;›; Assembly and listing control›;› .MACRO CHECK› .IF *<>%1› .ERROR "PC Mismatch"› .OPT LIST,MLIST›@TMP .= *-%1› .OPT NO LIST› LIST › .ENDIF› .ENDM›;›; LIST use current value of @LF›; LIST n set @LF=n and execute›; 0=no list 1=list 2=list+mlist›; 3=list+mlist+clist› .MACRO LIST› .IF %0=1›@LF .= %1› .ENDIF› .IF @LF› .IF @LF>2› .OPT CLIST› .ENDIF› .IF @LF>1› .OPT MLIST› .ENDIF› .OPT LIST› .ELSE› .OPT NO LIST,NO MLIST› .OPT NO CLIST› .ENDIF› .ENDM›